Abstract: Achieving better uniformity of temperature on an integrated circuit while performing burn-in can result in reduced burn-in time and more uniform acceleration. One way to achieve better temperature uniformity is to control dynamic power in the core and cache by operating at different frequencies and increasing switching activity in the cache(s) during burn-in by changing operation of the cache so that during burn-in a plurality of memory locations in the cache(s) are accessed simultaneously, thereby increasing activity in the cache to achieve higher power utilization in the cache during burn-in.

Abstract: A device is provided for detecting temperature-induced delays in a combinational logic path. A signal at the output of the logic path is latched at a first latch using a primary clock signal. The primary clock signal is delayed by a delay element to provide a delayed clock signal. The output of the logic path is latched at a second latch using the delayed clock signal. The delay element delays the clock signal by an amount that indicates the occurrence of an over-temperature condition at the logic path. A comparator compares the data latched at the first latch to the data latched at the second latch and provides an error signal indicative of an over-temperature condition if the first and second latch contain different data values.

Abstract: A device is provided for detecting delays of data due to over-temperature conditions, the device includes a first latch having a data input and a clock input and an output, and a first delay path including combinational logic, a first input coupled to the output of the first latch, and an output. The device further includes a second latch having a data input coupled to the output of the first delay path, a clock input coupled to the clock input of first latch, and an output, and a delay element having a data input coupled to the clock input of the first latch and an output. The device includes a third latch having a data input coupled to the output of the first delay path, a clock input coupled to the output of the delay element, and an output, and a comparator having a first input coupled to the output of the second latch, a second input coupled to the output of the third latch, and an output.

Abstract: Achieving better uniformity of temperature on an integrated circuit while performing burn-in can result in reduced burn-in time and more uniform acceleration. One way to achieve better temperature uniformity is to control dynamic power in the core and cache by operating at different frequencies and increasing switching activity in the cache(s) during burn-in by changing operation of the cache so that during burn-in a plurality of memory locations in the cache(s) are accessed simultaneously, thereby increasing activity in the cache to achieve higher power utilization in the cache during burn-in.

Abstract: An integrated circuit includes a first temperature sensing device providing an indication of a sensed temperature, a correlation oscillator circuit positioned adjacent to the first temperature sensing device, a plurality of other oscillator circuits, and storage locations storing calibration factors associated with at least the first temperature sensing device and the plurality of other oscillator circuits. A temperature calculation circuit determines temperatures of various locations in the integrated circuit. Each of the temperatures is determined according to an oscillation frequency of a respective one of the other oscillators, the oscillation frequency of the correlation ring oscillator, the temperature of the first temperature sensing device, and one or more stored calibration factors.

Abstract: A method and apparatus for conducting built-in self-timing tests. In one embodiment, a method for conducting timing tests includes selecting one or more I/O pairs (each I/O pair including a driver and a receiver) into a loop of a ring oscillator, the ring oscillator including an odd number of inverters. The ring oscillator is coupled to a measurement circuit configured to measure delay time in the loop. After initiating operation of the ring oscillator, the delay time through the loop can be measured. Selection circuits may be used to selectively enable or bypass individual I/O pairs in the loop of the ring oscillator. This selective bypassing may allow timing measurements for individual I/O pairs.

Abstract: The circuit to be used either to create a simultaneously switching outputs (SSO) event or to create a simultaneously switching inputs (SSI) event. The circuit uses a toggle register to generate a toggling signal and a signal line to operate logic to select the toggling signal as output from the circuit for the SSO event. The signal line is connected to an external pin. The circuit uses another signal line, also connected to an external pin, to disable or tristate the output driver that drives the I/O pin. This permits the circuit to receive input for the SSI event. Two chips, each having a plurality of such circuits, can be arranged so that one chip generates the SSO event and sends it to the second chip, which is configured to receive the SSI event. The circuit also has a pair of registers in a cascade arrangement to provide precise control of the output signal. The circuit has an additional register to disable the output driver and permit the circuit to receive input for a scan event.