Abstract: A vehicular autonomous driving system includes a time division multiplexed (TDM) bus, an autonomous driving (AD) controller coupled to the TDM bus, and a plurality of AD sensors coupled to the TDM bus. The AD sensors are configured to collect AD data and transmit collected AD data to the AD controller on the TDM bus in an assigned time slot at a first power level. A first AD sensor of the plurality of AD sensors is configured to, based upon collected AD data, detect an AD emergency event. In response to the detection, the first AD sensor is configured to transmit an AD emergency message on the TDM bus in a non-assigned time slot and at a second power level that exceeds the first power level. The AD sensor may transmit the AD emergency message in a particular sub-slot of the non-assigned time slot.

Abstract: A vehicular autonomous driving system includes a time division multiplexed (TDM) bus, an autonomous driving (AD) controller coupled to the TDM bus, and a plurality of AD sensors coupled to the TDM bus. The AD sensors are configured to collect AD data and transmit collected AD data to the AD controller on the TDM bus in an assigned time slot at a first power level. A first AD sensor of the plurality of AD sensors is configured to, based upon collected AD data, detect an AD emergency event. In response to the detection, the first AD sensor is configured to transmit an AD emergency message on the TDM bus in a non-assigned time slot and at a second power level that exceeds the first power level. The AD sensor may transmit the AD emergency message in a particular sub-slot of the non-assigned time slot.

Abstract: A vehicular autonomous driving system includes a time division multiplexed (TDM) bus, an autonomous driving (AD) controller coupled to the TDM bus, and a plurality of AD sensors coupled to the TDM bus. The AD sensors are configured to collect AD data and transmit collected AD data to the AD controller on the TDM bus in an assigned time slot at a first power level. A first AD sensor of the plurality of AD sensors is configured to, based upon collected AD data, detect an AD emergency event. In response to the detection, the first AD sensor is configured to transmit an AD emergency message on the TDM bus in a non-assigned time slot and at a second power level that exceeds the first power level. The AD sensor may transmit the AD emergency message in a particular sub-slot of the non-assigned time slot.

Abstract: A vehicular autonomous driving system includes a time division multiplexed (TDM) bus, an autonomous driving (AD) controller coupled to the TDM bus, and a plurality of AD sensors coupled to the TDM bus. The AD sensors are configured to collect AD data and transmit collected AD data to the AD controller on the TDM bus in an assigned time slot at a first power level. A first AD sensor of the plurality of AD sensors is configured to, based upon collected AD data, detect an AD emergency event. In response to the detection, the first AD sensor is configured to transmit an AD emergency message on the TDM bus in a non-assigned time slot and at a second power level that exceeds the first power level. The AD sensor may transmit the AD emergency message in a particular sub-slot of the non-assigned time slot.

Abstract: A vehicular autonomous driving system includes a time division multiplexed (TDM) bus, an autonomous driving (AD) controller coupled to the TDM bus, and a plurality of AD sensors coupled to the TDM bus. The AD sensors are configured to collect AD data and transmit collected AD data to the AD controller on the TDM bus in an assigned time slot at a first power level. A first AD sensor of the plurality of AD sensors is configured to, based upon collected AD data, detect an AD emergency event. In response to the detection, the first AD sensor is configured to transmit an AD emergency message on the TDM bus in a non-assigned time slot and at a second power level that exceeds the first power level. The AD sensor may transmit the AD emergency message in a particular sub-slot of the non-assigned time slot.

Abstract: A vehicular autonomous driving system includes a time division multiplexed (TDM) bus, an autonomous driving (AD) controller coupled to the TDM bus, and a plurality of AD sensors coupled to the TDM bus. The AD sensors are configured to collect AD data and transmit collected AD data to the AD controller on the TDM bus in an assigned time slot at a first power level. A first AD sensor of the plurality of AD sensors is configured to, based upon collected AD data, detect an AD emergency event. In response to the detection, the first AD sensor is configured to transmit an AD emergency message on the TDM bus in a non-assigned time slot and at a second power level that exceeds the first power level. The AD sensor may transmit the AD emergency message in a particular sub-slot of the non-assigned time slot.

Abstract: Poor transmission reliability is identified in a data channel. Multiple frequency carriers are used to transmit different sets of data within the data channel. A frequency bin is assigned to each frequency carrier. The frequency bins are used to provide data to each frequency carrier. A transmission power assigned to each frequency carrier may be insufficient to overcome noise in the data channel when all the frequency bins are used to transfer data concurrently. The number of frequency bins associated with frequency carriers of the data channel are reduced. Power is increased to the available frequency bins to improve transmission reliability. The available frequency bins are allocated across the data channel according to a pattern used to spread allocated transmission power across the data channel. The frequency bin pattern is rotated among available frequency bins of the data channel, allowing different frequency bins to be used for each transmission.

Abstract: A system and method for communicating with a plurality of devices are disclosed. One embodiment of the method includes transmitting a first plurality of sets of data on a plurality of data channels to a plurality of devices, wherein each of the first plurality of sets of data has a corresponding channel from the plurality of data channels and is transmitted to a corresponding device of the plurality of devices, and receiving a second plurality of sets of data on at least one of the plurality of data channels, wherein the second plurality of sets of data is sent by the plurality of devices, and wherein each of the second plurality of sets of data has a corresponding device of the plurality of devices. The second plurality of sets of data can include an acknowledgement from its corresponding device of the reception of at least one of the first plurality of data sets. Further, different channels of the plurality of data channels can include separate bands of frequencies.

Abstract: A method and apparatus for non-intrusive transceiver property adjustment are disclosed. One embodiment of the method for non-intrusive transceiver property adjustment comprises: determining a transceiver property to be adjusted, detecting a distortion event in a signal, and adjusting the transceiver property. The transceiver property can be determined based on a user input and/or on a predefined schedule. The predefined schedule can comprise a set of property limits (e.g., power level, frequency, gain, etc.). The signal can be an orthogonal frequency domain multiplexing (“OFDM”) signal or any signal having a phase change at a symbol boundary. The distortion event can comprise such a phase change at a symbol boundary. The adjusted transceiver property can comprise any time-domain changing property.

Abstract: A method and apparatus for producing multiple clock signals having controlled duty cycles and phase relationships includes processing that begins by generating a plurality of delayed clock signals from an input clock signal based on a delay control signal. The processing then continues by producing a first multiple clock signal from a first set of a plurality of delayed clock signals and the input clock signal. The processing then continues by producing a second multiplied clock signal from a second set of the plurality of delayed clock signals, where the second multiplied clock signal is delayed from the first multiplied clock signal in accordance with a delay of at least one of the delayed clock signals. The processing then continues by generating the delayed control signal based on the first multiplied clock signal, where the delay control signal controls delays of the plurality of delayed clock signals.

Abstract: In accordance with a specific embodiment of the present invention, a system is disclosed having an analog to digital converter and control module. The analog-to-digital converter includes an analog input, digital output, and control input. The control input of the analog-to-digital converter is connected to a pulse width modulated output of the control module which provides an offset pulse width modulated signal. During a first portion of the offset pulse width modulated signal a sampling capacitor is charged. During a second portion of the offset pulse width modulated signal an integration capacitor is charged.

Abstract: A method that includes the steps of producing a digital code (104) based at least in part on an integrated circuit capacitance and adjusting a frequency of the clocking signal in response to the digital code (106). A method that includes the steps of in a first mode of operation, producing a fixed frequency clocking signal, the fixed frequency clocking signal having a frequency tolerance less than 20 units per million and, in a second mode of operation, producing a variable frequency clocking signal, the variable frequency clocking signal having a frequency variability range greater than 200 units per million. An apparatus for providing a clocking signal includes a tuner circuit (12) and an oscillator circuit (16) responsive to the tuner circuit (12). The tuner circuit (12) is responsive to a clock signal source (38), an integrated circuit capacitance, and a reference resistor (18). The tuner circuit (12) produces a digital code signal.

Abstract: A capacitor (200) having an actual physical capacitance value of Cact and is coupled to an oscillator (36). The oscillation frequency of the oscillator (36) can be changed by changing the effective capacitance of the capacitor (200). The actual capacitance (Cact) of capacitor (200) can be altered to appear to be any effective capacitance (Ceff) between zero and a value much greater than Cact by using a Miller effect. In order to alter the effective capacitance of the capacitor (200), a representation of the output osculation signal (16) is provided to a frequency adjust stage (22). The frequency adjust stage either passed the signal (16) with 0.degree. phase shift or with 180.degree. phase shift. In addition to shifting the phase, the stage (22) will amplify or attenuate the signal (16) to result in the phase shifted and amplified/attenuated frequency adjusting signal (24).

Abstract: A frequency multiplication circuit (10) includes a periodic interval selector (12) and a delay element (28) to produce an output signal (26) in phase with, and at a frequency multiple of a reference signal (18). During a first time interval, the periodic interval selector (12) bases the output signal (26) on the reference signal (18). During a second time interval, the periodic interval selector (12) bases the output signal (26) on a delayed signal (22) produced by the delay element (14) based upon the output signal (26). Feedback from the output of the periodic interval selector (12) through the delay element (14) and the operation of the periodic interval selector (12) causes the output signal (26) to be in phase with, and at a frequency multiple of the reference signal (18). Delay adjuster (52) adjusts delay produced by the delay element (14) to adjust the output signal (26) to cause the output signal (26) to have a desired duty cycle consistency.

Abstract: A phase locked loop (10) with a phase detector (11), a digital loop filter (12), a digital controlled oscillator (13) and a divide-by-N circuit (14) generates a periodic signal which has a predetermined phase and voltage related to a reference clock signal. A phase and frequency detector (21) outputs an average of error between a feedback delay clock and a reference clock to the digital loop filter (12). The digital loop filter (12) processes the phase detector (11) output and the inband quantization noise utilizing a sigma delta converter. The digital loop filter (12) utilizes a non binary weight scheme to minimize the number of bits changing states. The digital controlled oscillator (13) generates a loop clock signal utilizing a plurality of digital programmable delay elements. A divide-by-N circuit (14) performs a divide by 2560.

Abstract: The output frequency (14) of an oscillator circuit (10) can be controlled by replacing at least one of the reactive components (40), such as a capacitor or inductor, with a synthesized element (22). The synthesized element creates a signal that corresponds to the response of the reactive component it is replacing. The synthesized element may be a current source (44), such as a field effect transistor, that is capable of operating at low voltages.

Abstract: A comparator (10) provides a high speed comparison between at least two input signals and includes at least two stages (12) and (14). Each stage (12 and 14) includes a pair of transistors (24), a complementary pair of transistors (28) and an enabling transistor (26). The stages are coupled to provide positive feedback back to the first stage (12). A controller (15) operably couples to the enabling transistors. When the first input signal (16) is at a higher voltage level than the second input signal (18), the first comparison output (20) goes low. Conversely, when the second input signal (18) is at a higher voltage level than the first input signal (16), the second comparison output (22) goes low. When the first comparison output (20) goes low, the second enabling transistor (34) is disabled by the controller (15). When the second comparison output goes low, the first enabling transistor (26) is disabled by the controller (15).

Abstract: A regulated supply (10) includes a charge pump (12), an output (14), a sensing circuit (16), and a control circuit (18). The charge pump (12) includes a variable capacitor (33) whose capacitance C.sub.v may be varied to compensate for changing loads and input power supply levels. The sensing circuit (16) senses the voltage level at the output (14) and provides feedback signals (66) and (68) to the control circuit (18). The voltage at the output (14) is dependent upon the capacitance C.sub.v of the variable capacitor (33). Therefore, responsive to the feedback signals (66) and (68) from the sensing circuit, the control circuit (18) varies the capacitance C.sub.v of the variable capacitor (33). The control circuit (18) then may vary the value of C.sub.v in a step-like manner to correct for the voltage at the output (14).