Abstract: A method and apparatus for producing multiple clock signals having controlled duty cycles and phase relationships includes processing that begins by generating a plurality of delayed clock signals from an input clock signal based on a delay control signal. The processing then continues by producing a first multiple clock signal from a first set of a plurality of delayed clock signals and the input clock signal. The processing then continues by producing a second multiplied clock signal from a second set of the plurality of delayed clock signals, where the second multiplied clock signal is delayed from the first multiplied clock signal in accordance with a delay of at least one of the delayed clock signals. The processing then continues by generating the delayed control signal based on the first multiplied clock signal, where the delay control signal controls delays of the plurality of delayed clock signals.

Abstract: In accordance with a specific embodiment of the present invention, a system is disclosed having an analog to digital converter and control module. The analog-to-digital converter includes an analog input, digital output, and control input. The control input of the analog-to-digital converter is connected to a pulse width modulated output of the control module which provides an offset pulse width modulated signal. During a first portion of the offset pulse width modulated signal a sampling capacitor is charged. During a second portion of the offset pulse width modulated signal an integration capacitor is charged.