Abstract: Embodiments of the present invention provide electrical bussing for multichip leadframes. In various embodiments, a leadframe may comprise a first die paddle for receiving a first microelectronic device, a second die paddle for receiving a second microelectronic device, and at least one electrical bus disposed between the first die paddle and the second die paddle.

Abstract: An integrated circuit or chip includes a first die and a second die positioned on a lead frame of a package including a lead frame, such as a QFP, DIP, PLCC, TSOP, or any other type of package including a lead frame. The integrated circuit further includes a redistribution layer formed on the first die to couple selected bond fingers of the lead frame to selected bonding pads of the first and second die. The selected bond fingers may correspond to bond fingers that receive a first supply voltage or the first supply voltage and a second supply voltage.

Abstract: Embodiments of the present invention provide leadframes including a die paddle including one or more apertures defined therein, and electronic packages employing the same and having a microelectronic device mounted on the die paddle over one or more of the apertures. Other embodiments may be described and claimed.

Abstract: Embodiments of the present invention provide electrical bussing for multichip leadframes. In various embodiments, a leadframe may comprise a first die paddle for receiving a first microelectronic device, a second die paddle for receiving a second microelectronic device, and at least one electrical bus disposed between the first die paddle and the second die paddle. In various ones of these embodiments, the electrical bus may be configured to supply a potential to at least one of the first and second microelectronic devices.

Abstract: A Quad Flat Pack (QFP) package which includes first and second dies arranged in a side-by-side orientation, and a power supply bus which protrudes between adjacent sides of the first and second dies and which supplies power to the adjacent sides via connections to the adjacent sides.

Abstract: An integrated circuit or chip includes a first die and a second die positioned on a lead frame of a package including a lead frame, such as a QFP, DIP, PLCC, TSOP, or any other type of package including a lead frame. The integrated circuit further includes a redistribution layer formed on the first die to couple selected bond fingers of the lead frame to selected bonding pads of the first and second die. The selected bond fingers may correspond to bond fingers that receive a first supply voltage or the first supply voltage and a second supply voltage.

Abstract: An integrated circuit including a copper interconnection layer includes an aluminum distribution layer overlying the copper interconnection layer to distribute external electrical signals such as power, ground, and clock signals throughout the die of the device. The distribution layer overlies the copper interconnection layer in a grid pattern which connects to the copper interconnection layer through a plurality of vias. The distribution layer further includes a plurality of wire bond pads to permit wire bonding between the distribution layer and bonding pads of the integrated circuit package.

Abstract: An improved bond pad on an integrated circuit has an elongated rectangular shape, on which the wire is bonded at a non-central location displaced toward an outer corner, so that there is room on the pad for a second bond site to be used for a rework bond. The pad corner closest to the path of a wire may be chamfered to reduce the distance of closest approach.

Abstract: The bond pads (22) for a ceramic package (10) are deposited on the pre-fired ceramic at variable pitch with the bond pad widths (47) increasing as a function of the distance (49) of each pad from an alignment point (40), whereby bond pads at the extremity (36) of the package have the largest pad width and pads toward the alignment point (40) of the package have the narrowest width.

Abstract: The bond pads (22) for a ceramic package (10) are deposited on the pre-fired ceramic with the bond pad widths (47) increasing as a function of the distance (49) of each pad from the center of package mass (40), whereby bond pads at the extremity (36) of the package have the largest pad width and pads toward the center (40) of the package have the narrowest width.

Abstract: A novel test die for emulating the thermal characteristics of functional product dies includes a plurality of concentric emulator ring configurations fabricated about the die center, each having a plurality of heating resistors approximately forming a rectangle, a plurality of sense diodes located in proximity to the heating resistors and a plurality of hot spot resistors located in proximity to both the heating resistors and the sense diodes. Metallic interconnections are formed on the die which selectively provide each of the heating resistors and hot spot resistors with excitation signals and present signals from the sense diodes indicative of the voltage thereacross.

Abstract: A leadframe assembly comprises a plurality of bifurcated leads, each characterized by an inner lead end region adapted for connection to the die bond pads and an outer lead end region adapted for connection to external circuitry.

Abstract: Disclosed is a method and an article formed thereby which includes a part which is subjected to heat during fabrication of an IC package, and a fixture for holding such a part, having an arrangement for accommodating the expansion and contraction of the part during heating and cooling while holding the part in alignment. In one embodiment, the expansion and contraction arrangement comprises slots arranged as apices of a triangle in the part which receives pins in the fixture with the major axes of the slots in alignment with the point of minimum expansion and contraction of the part. Utilizing the triangulation principle, the location of the datum hole (or locating criteria), if not at the point of minimum expansion and contraction of the part, can be effectively translated to the center of minimum expansion and contraction.