Patents by Inventor Michael D. Gruenhagen
Michael D. Gruenhagen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8598035Abstract: Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.Type: GrantFiled: June 2, 2011Date of Patent: December 3, 2013Assignee: Fairchild Semiconductor CorporationInventors: Michael D. Gruenhagen, Suku Kim, James J. Murphy, Eddy Tjhia, Chung-Lin Wu, Mark Larsen, Douglas E. Dolan
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Patent number: 8502313Abstract: This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.Type: GrantFiled: April 21, 2011Date of Patent: August 6, 2013Assignee: Fairchild Semiconductor CorporationInventors: Rohit Dikshit, Mark L. Rinehimer, Michael D. Gruenhagen, Joseph A. Yedinak, Tracie Petersen, Ritu Sodhi, Dan Kinzer, Christopher L. Rexer, Fred C. Session
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Patent number: 8338285Abstract: A semiconductor structure is formed as follows. Trenches are formed in a semiconductor region and a shield electrode is formed in each trench. Gate electrodes are formed in a portion of the trenches that form an active region. Each gate electrode is disposed over the shield electrode and is isolated from the shield electrode by an inter-electrode dielectric. An interconnect layer is formed extending over the trenches. The interconnect layer is isolated from the gate electrodes in the active region by a dielectric layer and contacts the shield electrodes in a shield contact region separate from the active region. The interconnect layer contacts mesa surfaces between adjacent trenches in the shield contact region.Type: GrantFiled: May 9, 2011Date of Patent: December 25, 2012Assignee: Fairchild Semiconductor CorporationInventors: Dixie Dunn, Paul Thorup, Dean E. Probst, Michael D. Gruenhagen
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Publication number: 20120267714Abstract: This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.Type: ApplicationFiled: April 21, 2011Publication date: October 25, 2012Inventors: Rohit Dikshit, Mark L. Rinehimer, Michael D. Gruenhagen, Joseph A. Yedinak, Tracie Petersen, Ritu Sodhi, Dan Kinzer, Christopher L. Rexer, Fred Session
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Publication number: 20120168947Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.Type: ApplicationFiled: February 24, 2012Publication date: July 5, 2012Inventors: Suku Kim, James J. Murphy, Michael D. Gruenhagen, Matthew R. Reynolds, Romel N. Manatad, Jan Vincent C. Mancelita
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Patent number: 8158506Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.Type: GrantFiled: May 5, 2008Date of Patent: April 17, 2012Assignee: Fairchild Semiconductor CorporationInventors: Suku Kim, James J. Murphy, Michael D. Gruenhagen, Matthew R. Reynolds, Romel N. Manatad, Jan Vincent C. Mancelita
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Patent number: 8072044Abstract: Methods for singulating a semiconductor wafer into a plurality of individual dies that contain lateral edges or sidewalls and the semiconductor dies formed from these methods are described. The dies are formed from methods that use a front to back photolithography alignment process to form a photo-resist mask and an anisoptropic wet etch in an HNA and/or a TMAH solution on the backside of the wafer through the photoresist mask to form sloped sidewalls and/or textures. The conditions of the TMAH etching process can be controlled to form any desired combination of rough or smooth sidewalls. Thus, the dies formed have a Si front side with an area larger than the Si backside area and sidewalls or lateral edges that are not perpendicular to the front or back surface of the die. Other embodiments are also described.Type: GrantFiled: September 17, 2009Date of Patent: December 6, 2011Assignee: Fairchild Semiconductor CorporationInventors: Michael D. Gruenhagen, Rohit Dikshit
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Patent number: 8058732Abstract: Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.Type: GrantFiled: November 20, 2008Date of Patent: November 15, 2011Assignee: Fairchild Semiconductor CorporationInventors: Michael D. Gruenhagen, Suku Kim, James J. Murphy, Ihsiu Ho, Eddy Tjhia, Chung-Lin Wu, Mark Larsen, Rohit Dikshit
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Publication number: 20110275208Abstract: A semiconductor structure is formed as follows. Trenches are formed in a semiconductor region and a shield electrode is formed in each trench. Gate electrodes are formed in a portion of the trenches that form an active region. Each gate electrode is disposed over the shield electrode and is isolated from the shield electrode by an inter-electrode dielectric. An interconnect layer is formed extending over the trenches. The interconnect layer is isolated from the gate electrodes in the active region by a dielectric layer and contacts the shield electrodes in a shield contact region separate from the active region. The interconnect layer contacts mesa surfaces between adjacent trenches in the shield contact region.Type: ApplicationFiled: May 9, 2011Publication date: November 10, 2011Applicant: Fairchild Semiconductor CorporationInventors: Dixie Dunn, Paul Thorup, Dean E. Probst, Michael D. Gruenhagen
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Publication number: 20110230046Abstract: Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.Type: ApplicationFiled: June 2, 2011Publication date: September 22, 2011Inventors: Michael D. Gruenhagen, Suku Kim, James J. Murphy, Eddy Tjhia, Chung-Lin Wu, Mark Larsen, Douglas E. Dolan
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Patent number: 7960800Abstract: Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.Type: GrantFiled: December 12, 2008Date of Patent: June 14, 2011Assignee: Fairchild Semiconductor CorporationInventors: Michael D. Gruenhagen, Suku Kim, James J. Murphy, Eddy Tjhia, Chung-Lin Wu, Mark Larsen, Douglas E. Dolan
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Patent number: 7952141Abstract: A semiconductor structure comprises an active region comprising trenches extending into a semiconductor region. Each trench includes a shield electrode and a gate electrode. The semiconductor structure also comprises a shield contact region adjacent to the active region. The shield contact region comprises at least one contact trench extending into the semiconductor region. The shield electrode from at least one of the trenches in the active region extends along a length of the contact trench. The semiconductor structure also comprises an interconnect layer extending over the active region and the shield contact region. In the active region the interconnect layer is isolated from the gate electrode in each trench by a dielectric layer and contacts mesa surfaces of the semiconductor region adjacent to the trenches. In the shield contact region the interconnect layer contacts the shield electrode and the mesa surfaces of the semiconductor region adjacent to the contact trench.Type: GrantFiled: July 24, 2009Date of Patent: May 31, 2011Assignee: Fairchild Semiconductor CorporationInventors: Dixie Dunn, Paul Thorup, Dean E. Probst, Michael D. Gruenhagen
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Publication number: 20110062564Abstract: Methods for singulating a semiconductor wafer into a plurality of individual dies that contain lateral edges or sidewalls and the semiconductor dies formed from these methods are described. The dies are formed from methods that use a front to back photolithography alignment process to form a photo-resist mask and an anisoptropic wet etch in an HNA and/or a TMAH solution on the backside of the wafer through the photoresist mask to form sloped sidewalls and/or textures. The conditions of the TMAH etching process can be controlled to form any desired combination of rough or smooth sidewalls. Thus, the dies formed have a Si front side with an area larger than the Si backside area and sidewalls or lateral edges that are not perpendicular to the front or back surface of the die. Other embodiments are also described.Type: ApplicationFiled: September 17, 2009Publication date: March 17, 2011Inventors: Michael D. Gruenhagen, Rohit Dikshit
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Publication number: 20110018059Abstract: A semiconductor structure comprises an active region comprising trenches extending into a semiconductor region. Each trench includes a shield electrode and a gate electrode. The semiconductor structure also comprises a shield contact region adjacent to the active region. The shield contact region comprises at least one contact trench extending into the semiconductor region. The shield electrode from at least one of the trenches in the active region extends along a length of the contact trench. The semiconductor structure also comprises an interconnect layer extending over the active region and the shield contact region. In the active region the interconnect layer is isolated from the gate electrode in each trench by a dielectric layer and contacts mesa surfaces of the semiconductor region adjacent to the trenches. In the shield contact region the interconnect layer contacts the shield electrode and the mesa surfaces of the semiconductor region adjacent to the contact trench.Type: ApplicationFiled: July 24, 2009Publication date: January 27, 2011Inventors: Dixie Dunn, Paul Thorup, Dean E. Probst, Michael D. Gruenhagen
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Publication number: 20110006409Abstract: Semiconductor devices containing nickel-titanium (NiTi or TiNi) compounds (or alloys) and methods for making such devices are described. The devices contain a silicon substrate with an integrated circuit having a drain on the backside of the substrate, a TiNi contact layer contacting the drain on the backside of the substrate, a soldering layer on the contact layer, an oxidation reducing layer on the soldering layer, a solder bump on the soldering layer, and a lead frame attached to the solder bump. The combination of the Ti and Ni materials in the contact layer exhibits many features not found in the Ti and Ni materials alone, such as reduced backside on-resistance, ability to form a silicide with the Si substrate at lower temperatures, reduced wafer warpage, increased ductility for improved elasticity, and good adhesion properties. Other embodiments are described.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Inventors: Michael D. Gruenhagen, James J. Murphy, Suku Kim, Jim Pierce, William S. Beggs, Robert J. Purtell
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Publication number: 20100148325Abstract: Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.Type: ApplicationFiled: December 12, 2008Publication date: June 17, 2010Inventors: Michael D. Gruenhagen, Suku Kim, James J. Murphy, Eddy Tjhia, Chung-Lin Wu, Mark Larsen, Douglas E. Dolan
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Publication number: 20100123225Abstract: Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.Type: ApplicationFiled: November 20, 2008Publication date: May 20, 2010Inventors: Michael D. Gruenhagen, Suku Kim, James J. Murphy, Ihsiu Ho, Eddy Tjhia, Chung-Lin Wu, Mark Larsen, Rohit Dikshit
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Publication number: 20090273082Abstract: Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described.Type: ApplicationFiled: May 5, 2008Publication date: November 5, 2009Inventors: Suku Kim, James J. Murphy, Michael D. Gruenhagen, Matthew R. Reynolds, Romel N. Manatad, Jan Vincent Mancelita