Patents by Inventor Michael D. Haddon

Michael D. Haddon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10670381
    Abstract: An electronic thermally-initiated venting system (ETIVS) for rocket motors includes at least one linear-shaped charge attached to a rocket motor housing. At least one exploding foil initiator (EFI) is attached to the linear-shaped charge. At least one electronic thermally-initiated venting system circuit is electrically-connected to the EFI. The EFI is configured to auto-fire when the electronic thermally-initiated venting system circuit relays a current pulse through the EFI. The linear-shaped charge is configured to initiate when the current pulse is relayed through the EFI.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: June 2, 2020
    Assignee: The United States of America, as Represented by the Secretary of the Navy
    Inventors: Paul E. Anderson, Michael D. Haddon
  • Patent number: 9915511
    Abstract: Embodiments are directed to unpowered railgun field validation for safe-arm fuzing. Embodiments use a wire coil having an induced electromotive force voltage. At least one positive duration circuit measures the positive portion of the induced voltage. At least one positive peak duration circuit measures the peak value of the positive portion of the induced voltage. At least one negative duration circuit measures the duration value of the negative portion of the induced voltage. At least one negative peak detector circuit measures the peak value of the negative portion of the induced voltage.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: March 13, 2018
    Assignee: The United States of America as Represented by the Secretary of the Navy
    Inventor: Michael D. Haddon
  • Patent number: 9625243
    Abstract: Embodiments relate to fuze setback validation. An electronic setback validator for a launched munition safe-arm fuze includes a transient voltage suppressor. A piezoceramic element is electrically-connected to the transient voltage suppressor. A first electronic circuit is electrically-connected to the piezoceramic element and is a constant 1 milliamp discharge circuit. The first electronic circuit is configured to determine setback magnitude of acceleration. A second electronic circuit is electrically-connected to the piezoceramic element. The second electronic circuit is a constant 122 microamp charge circuit and is configured to determine setback duration of acceleration. A microcontroller is electrically-connected to the first and second electronic circuits.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: April 18, 2017
    Assignee: The United States of America as Represented by the Secretary of the Navy
    Inventors: Michael D. Haddon, Paul E. Anderson
  • Patent number: 6782298
    Abstract: Electronics for a shock-hardened device, in particular a data recorder, incorporating non-volatile memory. The device has the functional elements: a signal conditioning circuit, an oscillator, an analog-to-digital converter (ADC), a field programmable gate array (FPGA), a trigger, and a non-volatile memory incorporating both electrically erasable programmable read only memory (EEPROM) and fast static random access memory (SRAM). As a recorder, the electronics enable efficient and reliable data recording in extreme shock environments, e.g., those involving dynamic testing of weapons such as target penetrating bombs or dual-stage warheads. It also provides for data retention upon loss or shutdown of power to the unit and yields high MTBF (mean time between failure) figures in more benign environments.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: August 24, 2004
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Gabriel H. Soto, Michael D. Haddon
  • Publication number: 20030223317
    Abstract: Electronics for a shock-hardened device, in particular a data recorder, incorporating non-volatile memory. The device has the functional elements: a signal conditioning circuit, an oscillator, an analog-to-digital converter (ADC), a field programmable gate array (FPGA), a trigger, and a non-volatile memory incorporating both electrically erasable programmable read only memory (EEPROM) and fast static random access memory (SRAM). As a recorder, the electronics enable efficient and reliable data recording in extreme shock environments, e.g., those involving dynamic testing of weapons such as target penetrating bombs or dual-stage warheads. It also provides for data retention upon loss or shutdown of power to the unit and yields high MTBF (mean time between failure) figures in more benign environments.
    Type: Application
    Filed: March 17, 2003
    Publication date: December 4, 2003
    Inventors: Gabriel H. Soto, Michael D. Haddon
  • Patent number: 6560494
    Abstract: Electronics for a shock-hardened device, in particular a data recorder, incorporating non-volatile memory. The device has the functional elements: a signal conditioning circuit, an oscillator, an analog-to-digital converter (ADC), a field programmable gate array (FPGA), a trigger, and a non-volatile memory incorporating both electrically erasable programmable read only memory (EEPROM) and fast static random access memory (SRAM). As a recorder, the electronics enable efficient and reliable data recording in extreme shock environments, e.g., those involving dynamic testing of weapons such as target penetrating bombs or dual-stage warheads. It also provides for data retention upon loss or shutdown of power to the unit and yields high mean time between failures (MTBF) figures in more benign environments.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: May 6, 2003
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Gabriel H. Soto, Michael D. Haddon
  • Patent number: 6389975
    Abstract: Disclosed, in a preferred embodiment, is a switching circuit incorporating a Field Effect Transistor (FET), two series dual-tap gas tube surge arrestors, and high-voltage resistors as part of a high voltage switch of a fireset for initiating an exploding foil initiator (EFI). Until energizing the FET via a firing command, an operating voltage of 1000 V is held off by a combination of the surge arrestors and high-voltage resistors. Upon receipt of a firing signal, a 28 V source is used to energize the FET that, in turn, decreases the voltage across the one surge arrestor connected directly to ground and increases the voltage across the other surge arrestor. Upon reaching the breakdown voltage of the ionizable gas within the second surge arrestor, the gas ionizes, becomes electrically conductive, and dumps the second surge arrestor's voltage across the first surge arrestor. This causes the first surge arrestor to also break down. Both surge arrestors are now conducting.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: May 21, 2002
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Michael D. Haddon, Gabriel H. Soto