Abstract: A multilayer identification patch comprises a reflective layer and a design layer on top of the reflective layer. The design layer comprises an opaque body and at least one identification symbol void (ISV) to allow light to reflect from a portion of the reflective layer via the ISV. The opaque body of the design layer comprises multiple layers of cured photopolymer ink. The multiple layers of cured photopolymer ink comprise an opaque layer of colored photopolymer ink. In one embodiment, the multiple layers of cured photopolymer ink in the opaque body of the design layer further comprise a layer of clear photopolymer ink under the opaque layer of colored photopolymer ink. Other embodiments are described and claimed.

Abstract: A multilayer identification patch comprises a reflective layer and a design layer on top of the reflective layer. The design layer comprises an opaque body and at least one identification symbol void (ISV) to allow light to reflect from a portion of the reflective layer via the ISV. The opaque body of the design layer comprises multiple layers of cured photopolymer ink. The multiple layers of cured photopolymer ink comprise an opaque layer of colored photopolymer ink. In one embodiment, the multiple layers of cured photopolymer ink in the opaque body of the design layer further comprise a layer of clear photopolymer ink under the opaque layer of colored photopolymer ink. Other embodiments are described and claimed.

Abstract: A laminated flip-chip interconnect package comprising a substrate having a chip attach surface and a board attach surface that define contact pads for attachment to corresponding pads on the chip and board wherein the substrate board surface comprises at least one solid plane covering the chip attach surface region near at least one chip corner. In one embodiment, the solid plane comprises a dielectric material, optionally covered with a soldermask or coverlay material. In an alternate embodiment, the solid plane comprises a metal, optionally covered with a soldermask or coverlay material.

Abstract: An interconnect module providing conductive interconnection paths between an integrated chip, a printed wiring board, and at least one layer within the module, incorporating a plurality of alternating dielectric and conductive layers laminated together to form a unitary structure. The module includes a chip attach surface and a board attach surface, that define contact pads for attachment to corresponding pads on the chip and printed wiring board, respectively, by means of solder balls.