Patents by Inventor Michael D. Jarchi

Michael D. Jarchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240137399
    Abstract: A method includes a method includes obtaining source data from a data source, the source data may correspond to a source clock and may be stored in a data buffer. The method may also include performing a clock adjustment to a determined clock. The determined clock may be associated with a data stream output from the data buffer. The clock adjustment may be operable to equalize the source clock and the determined clock. The method may include identifying a symbol clock associated with a buffer device. The method may also include adjusting an amount of null packets in the data stream, in response to a number of elements in the buffer device satisfying a threshold amount in the buffer device. The method may include updating clock reference values present in the source data such that a client device may synchronize with the source data with minimal clock jitter.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Applicant: MaxLinear, Inc.
    Inventors: Hang Jin, Pinaki Shankar Chanda, Michael D. Jarchi
  • Patent number: 9231798
    Abstract: Embodiments of the present invention analyze a plurality of parallel channels and identify specific channel(s) that have skew outside of an acceptable skew error margin. In certain embodiments, this skew is identified by determining the timing misalignment between a channel under test and a deskew channel. Other channels within the plurality of channels are masked by transmitting a repeating masked bit pattern. This timing misalignment may be measured by comparing a segment within the channel under test to a corresponding segment within the deskew channel and identifying a time differential between the two segments.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: January 5, 2016
    Assignee: Infinera Corporation
    Inventors: Ting-Kuang Chiang, Prasad Paranjape, Michael D. Jarchi, Mallikarjun Chillal
  • Patent number: 7570671
    Abstract: An apparatus and method for uniformly sharing across a plurality of channel signals FEC coding gain which may be achieved through FEC encoding of a higher baud rate electrical data signal or through multiplexed or combined electrical data signals from multiple data sources prior to their subsequent demultiplexing and separate generation into optical channel signals which are multiplexed and launched onto an optical transmission medium. The optical signal generation is achieved through reverse multiplexing of the higher baud rate data signal or of the multiplexed, FEC encoded plural data signals.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: August 4, 2009
    Assignee: Infinera Corporation
    Inventors: Drew D. Perkins, Michael D. Jarchi, Satish K. Sridharan
  • Publication number: 20090161247
    Abstract: Embodiments of the present invention analyze a plurality of parallel channels and identify specific channel(s) that have skew outside of an acceptable skew error margin. In certain embodiments, this skew is identified by determining the timing misalignment between a channel under test and a deskew channel. Other channels within the plurality of channels are masked by transmitting a repeating masked bit pattern. This timing misalignment may be measured by comparing a segment within the channel under test to a corresponding segment within the deskew channel and identifying a time differential between the two segments.
    Type: Application
    Filed: December 20, 2007
    Publication date: June 25, 2009
    Inventors: Ting-Kuang Chiang, Prasad Paranjape, Michael D. Jarchi, Mallikarjun Chillal
  • Patent number: 7146553
    Abstract: An enhanced forward error correction system is disclosed. Transmitted data is encoded into codewords in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes in each dimension, with corrected data provided as an output from each pass into another decoder for the next decode pass. The encoder in one embodiment comprises a parallel inner RS(247,239) encoder or encoders and parallel outer BCH(255,247) encoder or encoders. Additional steps are added for error multiplication reduction. The system provides an approach to detect generally uncorrectable patterns for concatenated codes and provides a correction mechanism for improving error correction performance.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: December 5, 2006
    Assignee: Infinera Corporation
    Inventors: Michael D. Jarchi, Satish K. Sridharan
  • Publication number: 20040096213
    Abstract: An apparatus and method for uniformly sharing across a plurality of channel signals FEC coding gain which may be achieved through FEC encoding of a higher baud rate electrical data signal or through multiplexed or combined electrical data signals from multiple data sources prior to their subsequent demultiplexing and separate generation into optical channel signals which are multiplexed and launched onto an optical transmission medium. The optical signal generation is achieved through reverse multiplexing of the higher baud rate data signal or of the multiplexed, FEC encoded plural data signals.
    Type: Application
    Filed: November 12, 2003
    Publication date: May 20, 2004
    Inventors: Drew D. Perkins, Michael D. Jarchi, Satish K. Sridharan
  • Publication number: 20030106009
    Abstract: An enhanced forward error correction system is disclosed. Transmitted data is encoded into codewords in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes in each dimension, with corrected data provided as an output from each pass into another decoder for the next decode pass. The encoder in one embodiment comprises a parallel inner RS(247,239) encoder or encoders and parallel outer BCH(255,247) encoder or encoders. Additional steps are added for error multiplication reduction. The system provides an approach to detect generally uncorrectable patterns for concatenated codes and provides a correction mechanism for improving error correction performance.
    Type: Application
    Filed: November 20, 2002
    Publication date: June 5, 2003
    Inventors: Michael D. Jarchi, Satish K. Sridharan
  • Publication number: 20030106013
    Abstract: An error correction system for coding codewords comprises a multi-symbol encoder and a multi-symbol decoder for respectively encoding codewords using a multi-symbol per clock and decoding codewords using a multi-symbol per clock. The multi-symbol encoder and decoder may employ Reed-Solomon codes for encoding and decoding process.
    Type: Application
    Filed: November 20, 2002
    Publication date: June 5, 2003
    Inventors: Michael D. Jarchi, Satish K. Sridharan