Abstract: Functional and geometrical sub-components of logic circuits are defined and used in the design of integrated circuits to facilitate the transformation of an integrated circuit design for fabrication at foundries with different design rules.

Abstract: A method of manufacturing an integrated circuit including adjusting a parameter of the operation of the integrated circuit, such as power dissipation, after prototype testing by changing only one mask. If prototype testing indicates that the performance specification for power dissipation, for example, is not met, the power dissipation can be adjusted by changing the size of the active areas to change the channel width of the gates of the circuit, by changing the size of the patterns of the active area masks. To decrease power dissipation, the size of the active area is decreased. Only the active mask need be changed. Preferably, the active area around the original contacts are maintained so that the positions of the contacts need not be changed. Consequently, the mask for defining the position of the contacts and the masks for defining the metallization layers need not be changed. To increase power dissipation, the size of the active areas is increased. The values of other parameters may be changed, as well.

Abstract: A high reliability logic circuit designed to withstand a single event upset (SEU) induced by an ion transitioning through a semiconductor structure is embodied in a memory circuit which includes a first memory cell and a second memory cell. The first and second memory cells receive a first input signal and a second input signal. The memory cells contain a logic circuit for producing a logic signal output driven by either a pullup or pulldown driver when the first and second input signals are of a desired logic state and produces a high impedance output if either input signal is not of their respective desired logic states.The memory cells also have sufficient nodal capacitance such that the output from the first or second memory cell will not be corrupted by an SEU in the logic circuit of either the first or second memory cell.The outputs of the first memory cell and second memory cell are further summed in analog fashion to produce a single output from the memory circuit.

Abstract: An interface controller, situated between a graphics controller and a memory array in a color video display system operable in a read-modify-write mode, configured to detect a select transparency color in whole or in part and to respond by selectively changing the color binary data for the corresponding pixel in a frame buffer. In another aspect, the invention includes drawing modes impelmented by logically combining pixel color binary data in accordance with a defined truth table so as to allow the pixel color data representing a new image to interact in a defined manner based upon color with the data in a previously defined image. As implemented, the binary data in the frame buffer is acted upon in a read-modify-write sequence whereby the various logic operations analyze the source (foreground) pixel data, the destination (background) pixel data, in the context of control signals, to define the pixel color data written into the frame buffer as the color representation for that pixel position.