Abstract: Semiconductor wafer (11) are uniformly and thoroughly cleaned of particulate and organic contaminants by sweeping the wafer with a hydraulic broom that sprays cleaning solution onto the wafer. The broom contains an aspirating nozzle (3) for connection to a source of pressurized gas, such as nitrogen, and to a source of cleaning fluid, such as acetone, wherein cleaning fluid aspirated by the gas stream is expressed through the nozzle outlet to impact the surface of the wafer, dislodging particulate matter and dissolving organic contaminants. A programmed controller (9) controls movement of the hydraulic broom relative to the wafer to ensure that the entire surface is cleaned and permits a variety of sweeping patterns.

Abstract: A method for forming relatively small vias in polymers which may have an underlying layer is disclosed. In a first embodiment, plated pillars are formed on a plated bottom metal layer. A polymer is coated over the first metal layer and the plated pillars and cured. The polymer is blanket etched to expose the top surface of the plated pillars. A metal layer is formed on top of the polymer layer and exposed surfaces of the plated pillars. In a second embodiment of the invention, pillars made from a photoresist are formed over a bottom metal layer. A polymer layer is coated over the pillars and the bottom metal layer and blanket etched to the surface of the photoresist pillar. The photoresist pillars are then removed forming vias. A top metal layer is formed on top of the polymer coating in the vias to connect to the bottom metal layer.

Abstract: Semiconductor wafer (11) are uniformly and thoroughly cleaned of particulate and organic contaminants by sweeping the wafer with a hydraulic broom that sprays cleaning solution onto the wafer. The broom contains an aspirating nozzle (3) for connection to a source of pressurized gas, such as nitrogen, and to a source of cleaning fluid, such as acetone, wherein cleaning fluid aspirated by the gas stream is expressed through the nozzle outlet to impact the surface of the wafer, dislodging particulate matter and dissolving organic contaminants. A programmed controller (9) controls movement of the hydraulic broom relative to the wafer to ensure that the entire surface is cleaned and permits a variety of sweeping patterns.

Abstract: A method for controlling the sheet resistance of thin film resistors. The sheet resistance can be inexpensively controlled within a tight tolerance by determining a desired final value for the sheet resistance of thin film resistor material to be deposited on a substrate, depositing the resistor material on the substrate using a deposition process which is consistent enough to achieve a target sheet resistance within a first specified tolerance, the resistor material being deposited to achieve a target sheet resistance which is equal to the desired final value minus the first specified tolerance, and removing a small amount of material from the surface of the deposited thin film resistor material by etching or ion bombardment to raise the sheet resistance to the desired final value within a second specified tolerance characteristic of the removing process where the second specified tolerance is less than the first specified tolerance.

Abstract: A method for controlling the sheet resistance of thin film resistors. The sheet resistance can be inexpensively controlled within a tight tolerance by determining a desired final value for the sheet resistance of thin film resistor material to be deposited on a substrate, depositing the resistor material on the substrate using a deposition process which is consistent enough to achieve a target sheet resistance within a first specified tolerance, the resistor material being deposited to achieve a target sheet resistance which is equal to the desired final value minus the first specified tolerance, and removing a small amount of material from the surface of the deposited thin film resistor material by etching or ion bombardment to raise the sheet resistance to the desired final value within a second specified tolerance characteristic of the removing process where the second specified tolerance is less than the first specified tolerance.

Abstract: A method of fabricating an HBT transistor with extremely high speed and low operating current. The transistor has a small base area and a small emitter area with most of the emitter area contacted with metal, most of the base area, outside of the emitter, contacted with metal and a collector ohmic metal placed close to the device emitter and the base ohmic metal. To achieve this, the method includes partially undercutting the base ohmic metal along all external edges to reduce the device's parasitic base-collector capacitance. In order to provide metal step coverage, the undercut of the base ohmic metal can be covered with a sloped edge polymer. In addition, a Schottky diode can be fabricated within the process steps used to form the HBT transistor without additional process steps being needed to build the Schottky diode.

Abstract: An RF switch and a process for fabricating an RF switch which includes multiple throws and can be fabricated utilizing only a single layer of metallization. The switch in accordance with the present invention includes an airbridge suspended beam disposed adjacent to one or more metal traces. One or more control pads are disposed adjacent to the airbridged suspended beam to operate the switch electrostatically. The suspended beam as well as the metal traces and contact pads are all fabricated with a single metallization layer. The switch is configured such that deflection of the beam is in a plane generally parallel to the plane of the substrate. By eliminating multiple metallization layers, the complexity for fabricating the switch is greatly reduced. Moreover, the switch configuration also allows multiple throws and multiple poles using a single level of metallization.

Abstract: A relatively simple method for providing relatively close spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) on a relatively uniform basis. An emitter and base layer are epitaxially grown on a substrate. An emitter mesa is patterned with an i-line negative photoresist using conventional photolithography. Baking before and after exposure is used to form a resist pattern with a re-entrant profile having about a 0.1 .mu.m resist overhang. The emitter layer is then etched with a wet etch and or isotropic dry etch to expose a portion of the base ohmic metal to make contact with the base. A second layer of an i-line negative photoresist is applied over the first photoresist. The second layer is used to pattern the base ohmic metal mask. The base ohmic metal is deposited by evaporation.

Abstract: A method for forming an airbridge for interconnecting metal contacts on an integrated circuit. The airbridge is formed by initially patterning a support photoresist between the metal contacts to be interconnected, over the metal contact to be crossed. The pattern support photoresist is flood exposed with UV light and subsequently baked at a relatively high temperature to cause the support photoresist to flow into a generally spherical shape. The airbridged metal lines are patterned over the spherically shaped support photoresist. Excess metallization is lifted off the support photoresist and the photoresist used to pattern the airbridge is removed, forming an airbridge with curvature along both its width and length.

Abstract: A method for controlling the spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) to obtain a relatively high gain (.beta.) with a low-parasitic base resistance. In a first method, after the emitter, base and collector layers are epitaxially grown on a substrate, a sacrificial layer is deposited on top of the emitter layer. The emitter mesa is patterned with a photoresist using conventional lithography. Subsequently, the sacrificial layer is etched to produce an undercut. The emitter layer is then etched and a photoresist is applied over the first photoresist used to pattern the emitter mesa, as well as the entire device. The top layer of photoresist is patterned with a conventional process for lift-off metalization, such that the final resist profile has a re-entrant slope. The base ohmic metal is deposited and then lifted off by dissolving both the second layer of photoresist, as well as the original photoresist over the emitter mesa.

Abstract: A method for forming an airbridge for interconnecting metal contacts on an integrated circuit. The airbridge is formed by initially patterning a support photoresist between the metal contacts to be interconnected, over the metal contact to be crossed. The pattern support photoresist is flood exposed with UV light and subsequently baked at a relatively high temperature to cause the support photoresist to flow into a generally spherical shape. The airbridged metal lines are patterned over the spherically shaped support photoresist. Excess metallization is lifted off the support photoresist and the photoresist used to pattern the airbridge is removed, forming an airbridge with curvature along both its width and length.

Abstract: A method of forming closely spaced metal electrodes contacting different regions of a semiconductor device is disclosed. The method includes first depositing a sacrificial layer over a developing semiconductor structure. Next, a photoresist layer is deposited over the sacrificial layer and then patterned and developed with a re-entrant profile opening. An opening in the dielectric layer is formed to expose a first semiconductor layer through the re-entrant profile using an anisotropic etch. The photoresist opening is enlarged by removing a portion of the photoresist layer. Then, a metal layer is deposited over the entire structure such that the metal contacts the first semiconductor layer and extends over a portion of the sacrificial layer. The photoresist layer, the sacrificial layer and portions of the first semiconductor layer are removed so that a first metal electrode is connected to a semiconductor region.

Abstract: This invention discloses a process by which a silicon bipolar transistor can be fabricated having a polysilicon emitter region and a polysilicon base region by a single polysilicon deposition step. After conventional fabrication of the substrate, collector and base layers, a first dielectric layer is deposited over the developing wafer structure. The first dielectric layer is then etched in order to define polysilicon emitter, base and collector regions. Next, a polysilicon layer is deposited over the first dielectric layer and the etched regions. A planarization layer is deposited over the polysilicon layer, and the planarization layer and the polysilicon layer are etched so that polysilicon only remains in the defined polysilicon emitter, base and collector regions. The polysilicon emitter, base and collector regions are then implanted with dopants to provide the appropriate interfaces.

Abstract: A low collector parasitic resistance in bipolar transistors may be achieved without the use of an epitaxial layer or a high energy implant. Essentially, the invention employs the use of trenches in an N.sup.- layer overlying a P.sup.- substrate to surround the transistor, forming an N.sup.+ region in the walls defining the trench and below the surface, extending the trench into the P.sup.- substrate, implanting the bottom of the trench with a P-type dopant and refilling the trench with insulating material.The process of the invention permits fabrication of complex bipolar integrated circuits having a very high performance, and is particularly adaptable to very small geometry devices of 1 .mu.m and lower.