Abstract: A cache memory (35) has a logical organisation in which its memory space is divided into sub-sections or partitions (P). This permits different data objects to be allocated to different partitions during the operation of the cache memory (35). Commands led used by the cache memory (10) may contain an extra parameter which is used to identify the appropriate partition within the cache memory (35). The parameter is extracted from the command by a decoder (37) and is passed to a specific line of an equator set (38) which contains identifiers which determine the partition to be used. To minimise data collisions for a given partition size, a stride may be defined which expresses the separation of addresses and from which a mapping function can be selected which covers all addresses in the cache memory (35) in an efficient way.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronization and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronization and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: A microcomputer includes an on-chip processor with at least 1K bytes of high density RAM on-chip together with isolation regions to protect the RAM from noise from transistors on-chip operating independently of the RAM.

Abstract: A method of routing messages through a network is described in which a message packet is dispatched with two node indicators through the network including a succession of routing switches. When the message packet reaches a routing switch identified by the first node indicator, that routing switch deletes the first node indicator and the second node indicator is then used to route the message packet through the network.

Abstract: A method of encoding data for transmission between computer devices is disclosed in which data is encoded into a plurality of sequences, each sequence containing an equal number of ones and zeros and being of a predetermined bit length. There is a finite set of the permutations of equal numbers of ones and zeros in that predetermined bit length. One subset of the finite set is selected for use as data codes and a second subset is selected for use as control codes.

Abstract: A routing switch includes an input for receiving serial packets from a source node in a computer network, a plurality of outputs each designating a respective range of destination node identifications, switch circuitry for selectively interconnecting said input to a selected one of said outputs and header reading circuitry for reading the header portion of a packet received at the input prior to receiving all of the packet. The header reading circuitry is coupled to the switch circuitry to connect to said input one of said outputs having a node identification range including the node identification of said header portion.There is also provided a computer network, having a plurality of computer devices and at least one routing switch, and a method of routing messages through such a network.

Abstract: A routing switch includes an input for receiving serial packets from a source node in a computer network, a plurality of outputs, switch circuitry for selectively interconnecting said input to a selected one of said outputs and header reading circuitry for reading the header portion of a packet received at the input prior to receiving all of the packet. The switch also has a random header generator which produces header portions generated at random which are then read by the header reading circuitry. The header reading circuitry is coupled to the switch circuitry to connect to said input one of said outputs in dependence on said random header. The random header portion is then discarded at the routing switch identified thereby to reveal the original header.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks or microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: A microcomputer has a processor arranged to share its time between a plurality of concurrent processes. Each process may have means (69) for indicating a time when the process may be executed. The processes may form a linked list of processes (T, U. V) awaiting scheduling for execution. A location (90) is provided for indicating the beginning of a timer list of processes awaiting execution and means (68) is provided for indicating the end of a timer list. The microcomputer may provide more than one timer list of processes of different priority. Each process may include a number of alternative components one or more of which is time dependent.

Abstract: Single chip microcomputers with program stored in on-chip RAM combined by non-shared communication links each having an input channel and an output channel, each channel having a data register and process register used for synchronizing processes executed in different microcomputers in an array. Each process on a chip has a workspace. Constant bit size instructions have function and data portions. Scheduling/descheduling of processes in each microcomputer occur by forming a linked list in the workspaces for active processs. Each workspace identifies the next process to be executed and the next instructon for its own process.

Abstract: A digital switch for selectively interconnecting a plurality of devices, including microcomputers, in a network comprises a plurality of inputs, a plurality of outputs and selectively operable interconnections which include decoding means for decoding data and acknowledgement bit packets, clock means, and means for generating under control of clock signals output bit packets having bit signals corresponding to bits of input bit packets.

Abstract: A microcomputer comprising memory and processor is arranged to execute a plurality of concurrent processes and share its time between them. The microcomputer includes means for indicating a current process as well as a collection of processes awaiting execution. Processes may be added to the collection. Next process indicating means is provided to indicate the next process to be executed. Synchronization means is provided to synchronize communication between concurrent processes on the same microcomputer or interconnected microcomputers. The synchronization means may schedule a process by adding it to the collection or terminating execution of the current process.

Abstract: A communication interface for effecting communication by serial bit packets on unidirectional non-shared lines comprises a packet generator 70 arranged to output a byte of data in a data packet of a first format or an acknowledgement packet of a second format and a packet decoder 71 is arranged to decode incoming packets.

Abstract: A microcomputer comprising memory 60 and a process is arranged to execute a plurality of concurrent processes and share its time between them. The microcomputer includes as register (51) for indicating a current process as well as a collection of processes awaiting execution. Each process has a memory location 66 to provide an indication of a next process in a linked list of processes. Each process has an allocated priority and a separate linked list is formed for each priority. A register (53) indicates the front of one list and a further register (52) indicates the end of that list.

Abstract: A microcomputer method and system for executing a plurality of concurrent processes provides synchronized message transmission so that data is transmitted between a communicating pair of processes when the two processes are at corresponding program stages. The messages may be variable in length and are transmitted by indicating a source address for the data to be transmitted, a destination address for the data, and a count of the number of standard unit lengths of data to be transmitted in the message.

Abstract: A microcomputer comprises memory (60) and a processor including a plurality of channels (70) to enable data transmission between concurrent processes. An inputting process may input data through one of a plurality of alternative input channels (70). Data transmission occurs when both processes are at corresponding stages in their programs. If an inputting process finds that no outputting process is yet ready on any of the alternative channels the inputting process may be descheduled and synchronisation achieved by special values located in locations (67) in a workspace (60) for the process.

Abstract: A programmable, high speed, single chip microcomputer includes 4K of RAM, ROM, registers and an ALU. Program can be stored in the on-chip RAM. The first local variable of each process to be executed is a workspace pointer (WPTR), and each process has a respective workspace identified by its WPTR. For each process, addressing of other variables is relative to the current WPTR, which is stored in a workspace pointer register (WPTR REG). Instructions are constant bit size, having a function portion and a data portion loaded, respectively, into an instruction buffer (IB) and an operand register (OREGTR). Memory address locations are formed by combining the contents of the workspace pointer register and the operand register, or the contents of the A Register and the operand register. A set of "direct functions" obtains data from OREG. "Indirect functions" use the OREG contents to identify other functions, obtaining data from registers other than the operand register.

Abstract: A programmable, high speed, single chip microcomputer includes 4K of RAM, ROM, registers and an ALU. Program can be stored in the on-chip RAM. The first local variable of each process to be executed is a workspace pointer (WPTR), and each process has a respective workspace identified by its WPTR. For each process, addressing of other variables is relative to the current WPTR, which is stored in a workspace pointer register (WPTR REG). Instructions are constant bit size, having a function portion and a data portion loaded, respectively, into an instruction buffer (IB) and an operand register (OREGTR). Memory address locations are formed by combining the contents of the workspace pointer register and the operand register, or the contents of the A Register and the operand register. A set of "direct functions" obtains data from OREG. "Indirect functions" use the OREG contents to identify other functions, obtaining data from registers other than the operand register.

Abstract: A microcomputer system with a processor and memory operates concurrent processes with synchronized communication between pairs of processes. Each communicating process has program instructions including one communication instruction to output or input data. The processes executed by a processor are scheduled by identifying a collection awaiting execution and descheduled by interrupting execution of instructions by the process. A communication channel is used to hold a value indicating whether or not either of a pair of communicating processes has yet executed an instruction requiring communication through that channel. Each communicating process tests the channel contents, and if the other communicating process has not yet reached the corresponding communication instruction, the process is descheduled until both processes have reached corresponding program stages.