Abstract: Multi-way partitioning is dramatically improved based on “weakest-link” optimality. The set of numbers to be partitioned is subjected to pairwise decomposition with a first partition having a candidate subset (P1={S1}), and a lower cost bound cmin is set equal to a maximum cost of this subset. A recursive call is then invoked to resolve the subproblem of the second partition (P2={S2, S3, . . . , Sk}). If each second candidate subset in the second partition has a cost which is less than or equal to the lower cost bound, then the first partition is returned with the second partition as an optimal solution regardless of whether the second partition is an optimal decomposition. Additional efficiency may be achieved by excluding any subset having a cost which is greater than or equal to the best cost so far. Dominated and symmetric solutions can also be excluded.

Abstract: Multi-way partitioning is dramatically improved based on “weakest-link” optimality. The set of numbers to be partitioned is subjected to pairwise decomposition with a first partition having a candidate subset (P1={S1}), and a lower cost bound cmin is set equal to a maximum cost of this subset. A recursive call is then invoked to resolve the subproblem of the second partition (P2={S2, S3, . . . , Sk}). If each second candidate subset in the second partition has a cost which is less than or equal to the lower cost bound, then the first partition is returned with the second partition as an optimal solution regardless of whether the second partition is an optimal decomposition. Additional efficiency may be achieved by excluding any subset having a cost which is greater than or equal to the best cost so far. Dominated and symmetric solutions can also be excluded.

Abstract: Multi-way partitioning is dramatically improved based on “weakest-link” optimality. The set of numbers to be partitioned is subjected to pairwise decomposition with a first partition having a candidate subset (P1={S1}), and a lower cost bound cmin is set equal to a maximum cost of this subset. A recursive call is then invoked to resolve the subproblem of the second partition (P2={S2, S3, . . . , Sk}). If each second candidate subset in the second partition has a cost which is less than or equal to the lower cost bound, then the first partition is returned with the second partition as an optimal solution regardless of whether the second partition is an optimal decomposition. Additional efficiency may be achieved by excluding any subset having a cost which is greater than or equal to the best cost so far. Dominated and symmetric solutions can also be excluded.

Abstract: Multi-way partitioning is dramatically improved based on “weakest-link” optimality. The set of numbers to be partitioned is subjected to pairwise decomposition with a first partition having a candidate subset (P1={S1}), and a lower cost bound cmin is set equal to a maximum cost of this subset. A recursive call is then invoked to resolve the subproblem of the second partition (P2={S2, S3, . . . , Sk}). If each second candidate subset in the second partition has a cost which is less than or equal to the lower cost bound, then the first partition is returned with the second partition as an optimal solution regardless of whether the second partition is an optimal decomposition. Additional efficiency may be achieved by excluding any subset having a cost which is greater than or equal to the best cost so far. Dominated and symmetric solutions can also be excluded.

Abstract: Methods, systems, and computer program products may provide planning for hardware-accelerated functional verification in data processing systems. A method may include receiving, by a computer system, a description of architecture of a hardware accelerator for accelerating functional verification of a circuit design, the architecture including a plurality of logical processors. The method may additionally include receiving, by the computer system, a description of the circuit design having a plurality of gates, and representing, by the computer system, each gate, each stage of the functional verification, and each logical processor as a separate object based on the received description of the architecture and the circuit design.

Abstract: Methods, systems, and computer program products may provide planning for hardware-accelerated functional verification in data processing systems. A method may include receiving, by a computer system, a description of architecture of a hardware accelerator for accelerating functional verification of a circuit design, the architecture including a plurality of logical processors. The method may additionally include receiving, by the computer system, a description of the circuit design having a plurality of gates, and representing, by the computer system, each gate, each stage of the functional verification, and each logical processor as a separate object based on the received description of the architecture and the circuit design.

Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

Abstract: A circuit design is compiled for hardware-accelerated functional verification by removing internal gates of a uniform operator tree (e.g., an assertion tree) while retaining node information, and partitioning the circuit to optimize connectivity without being constrained by the uniform operator tree. After partitioning, sub-trees are constructed for the partitions, and aggregated to form a master tree. The sub-trees can have leaf nodes at varying depths based on ranks of the leaf nodes, and the master tree can similarly provide inputs from the sub-trees at varying depths based on simulation depths for the sub-trees. The resynthesized master tree is structurally distinct from the original uniform operator tree but, since the inputs are commutative (e.g., OR gates), the functional equivalence of the model is preserved.

Abstract: A circuit design is compiled for hardware-accelerated functional verification by removing internal gates of a uniform operator tree (e.g., an assertion tree) while retaining node information, and partitioning the circuit to optimize connectivity without being constrained by the uniform operator tree. After partitioning, sub-trees are constructed for the partitions, and aggregated to form a master tree. The sub-trees can have leaf nodes at varying depths based on ranks of the leaf nodes, and the master tree can similarly provide inputs from the sub-trees at varying depths based on simulation depths for the sub-trees. The resynthesized master tree is structurally distinct from the original uniform operator tree but, since the inputs are commutative (e.g., OR gates), the functional equivalence of the model is preserved.

Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

Abstract: A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions.

Abstract: A portion of a gate-level netlist representing an integrated circuit design is selected for optimization. A timing window representing the selected portion is made comprising one or more copies of the selected portion. A checkpoint is created for the timing window and stored in a transaction history. One or more changes are then made to the timing window and stored in the transaction history. The changed elements are marked as dirty and stored in the transaction history. After the one or more changes have been made, the timing window is queried for current timing conditions and compared with the checkpoint. If the one or more changes are an improvement, the one or more changes are committed by replicating the one or more changes to the portion of the gate-level netlist. If the one or more changes are not an improvement, the timing window may be restored to the checkpoint.

Abstract: The present disclosure is directed to a method for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net. The method may comprise estimating a total wire capacitance; calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks; and estimating the interconnect delay for the source-to-sink path based on the delay contribution.

Abstract: The present disclosure is directed to a method for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net. The method may comprise estimating a total wire capacitance; calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks; and estimating the interconnect delay for the source-to-sink path based on the delay contribution.

Abstract: A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Path Smoothing utility identifies one or more movable gates based on at least one selection criteria. A set of legalized candidate locations corresponding to one or more identified movable gates is generated. A disjunctive timing graph based on the generated set of legalized candidate locations is then generated. An optimal location of one or more movable gate(s) is determined using a recursive branch-and-bound search and stored in the computing device.

Abstract: A portion of a gate-level netlist representing an integrated circuit design is selected for optimization. A timing window representing the selected portion is made comprising one or more copies of the selected portion. A checkpoint is created for the timing window and stored in a transaction history. One or more changes are then made to the timing window and stored in the transaction history. The changed elements are marked as dirty and stored in the transaction history. After the one or more changes have been made, the timing window is queried for current timing conditions and compared with the checkpoint. If the one or more changes are an improvement, the one or more changes are committed by replicating the one or more changes to the portion of the gate-level netlist. If the one or more changes are not an improvement, the timing window may be restored to the checkpoint.

Abstract: A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Path Smoothing utility identifies one or more movable gates based on at least one selection criteria. A set of legalized candidate locations corresponding to one or more identified movable gates is generated. A disjunctive timing graph based on the generated set of legalized candidate locations is then generated. An optimal location of one or more movable gate(s) is determined using a recursive branch-and-bound search and stored in the computing device.

Abstract: A system for compressing information arranges unprocessed information into a plurality of data planes. The data planes are converted into a combined planar data output. The combined planar data output is created by regrouping data elements which make up the unprocessed information. The regrouping is such that the entropy of the unprocessed information is increased. This provides increased compressibility of the data. The combined planar data output is compressed using standard information compression techniques. Data is reconstructed by uncompressing compressed data and rearranging it into its original format.

Abstract: A system for compressing information arranges unprocessed information into a plurality of data planes. The data planes are converted into a combined planar data output. The combined planar data output is created by regrouping data elements which make up the unprocessed information. The regrouping is such that the entropy of the unprocessed information is increased. This provides increased compressibility of the data. The combined planar data output is compressed using standard information compression techniques. Data is reconstructed by uncompressing compressed data and rearranging it into its original format.