Abstract: A method for implementing pattern matching of integrated circuit features includes computing Voronoi edge regions for both a reference configuration and a search space of an integrated circuit design to be searched and presenting the computed Voronoi edge regions of the reference configuration to a user; receiving one or more selected bisectors of the Voronoi computed reference configuration from the user, indicative of user identified salient regions of design shapes and/or corners to be searched, so as to define one or more search elements, wherein a search element comprises a given bisector and a pair of Voronoi edge regions bounded thereby; constructing a search pattern from the one or more search elements defined from the reference configuration; examining the search space for matching sequences with respect to the search pattern; and highlighting resulting matching patterns in the search space for the user.

Abstract: A method for implementing integrated circuit yield estimation includes computing Voronoi regions for an original integrated circuit layout; for each bisector segment of the Voronoi regions and one or more failure mechanisms, computing a failure probability based on geometric parameters of corresponding Voronoi edge regions associated with the bisector segment, using pre-computed failure probabilities as a function of edge orientation and spacing for the failure mechanisms; for each segment of a design edge bounded by bisectors, computing a change in the failure probability based on the geometric parameters of the Voronoi regions, using pre-computed change in failure probabilities for the failure mechanisms; encoding the computed failure probabilities for each Voronoi region in a manner suitable for visual differentiation by a user; and encoding the computed change in failure probabilities by directional displacement of a layout edge segment that would result in a decrease in failure probability.

Abstract: Methods and arrangements for generating a voice model in speech processing. Upon accepting at least two input vectors with spectral features, vectors of ranks are created via ranking values of the spectral features of each input vector, ordered vectors are created via arranging the values of each input vector according to rank, and a vector of ordered average values is created via determining the average of corresponding values of the ordered vectors. Thence, a vector of ordered average ranks is created via determining the sum or average of the vectors of ranks, a vector of ordered ranks is created via ranking the values of the ordered average ranks and a spectral feature vector is created via employing the rank order represented by the vector of ordered ranks to reorder the vector of ordered average ranks.

Abstract: A method for implementing integrated circuit yield estimation includes computing Voronoi regions for an original integrated circuit layout; for each bisector segment of the Voronoi regions and one or more failure mechanisms, computing a failure probability based on geometric parameters of corresponding Voronoi edge regions associated with the bisector segment, using pre-computed failure probabilities as a function of edge orientation and spacing for the failure mechanisms; for each segment of a design edge bounded by bisectors, computing a change in the failure probability based on the geometric parameters of the Voronoi regions, using pre-computed change in failure probabilities for the failure mechanisms; encoding the computed failure probabilities for each Voronoi region in a manner suitable for visual differentiation by a user; and encoding the computed change in failure probabilities by directional displacement of a layout edge segment that would result in a decrease in failure probability.

Abstract: A method for implementing pattern matching of integrated circuit features includes computing Voronoi edge regions for both a reference configuration and a search space of an integrated circuit design to be searched and presenting the computed Voronoi edge regions of the reference configuration to a user; receiving one or more selected bisectors of the Voronoi computed reference configuration from the user, indicative of user identified salient regions of design shapes and/or corners to be searched, so as to define one or more search elements, wherein a search element comprises a given bisector and a pair of Voronoi edge regions bounded thereby; constructing a search pattern from the one or more search elements defined from the reference configuration; examining the search space for matching sequences with respect to the search pattern; and highlighting resulting matching patterns in the search space for the user.

Abstract: A system, method and program product for searching and classifying patterns in a VLSI design layout. A method is provided that includes generating a target vector using a two dimensional (2D) low discrepancy sequence; identifying layout regions in a design layout; generating a feature vector for a layout region; comparing a subset of sequence values in the target vector with sequence values in the feature vector as an initial filter, wherein the system for comparing determines that the layout region does not contain a match if a comparison of the subset of sequence values in the target vector with sequence values in the feature vector falls below a threshold; and outputting search results.

Abstract: Methods and arrangements for generating a voice model in speech processing. Upon accepting at least two input vectors with spectral features, vectors of ranks are created via ranking values of the spectral features of each input vector, ordered vectors are created via arranging the values of each input vector according to rank, and a vector of ordered average values is created via determining the average of corresponding values of the ordered vectors. Thence, a vector of ordered average ranks is created via determining the sum or average of the vectors of ranks, a vector of ordered ranks is created via ranking the values of the ordered average ranks and a spectral feature vector is created via employing the rank order represented by the vector of ordered ranks to reorder the vector of ordered average ranks.

Abstract: Methods and arrangements for generating a voice model in speech processing. Upon accepting at least two input vectors with spectral features, vectors of ranks are created via ranking values of the spectral features of each input vector, ordered vectors are created via arranging the values of each input vector according to rank, and a vector of ordered average values is created via determining the average of corresponding values of the ordered vectors. Thence, a vector of ordered average ranks is created via determining the sum or average of the vectors of ranks, a vector of ordered ranks is created via ranking the values of the ordered average ranks and a spectral feature vector is created via employing the rank order represented by the vector of ordered ranks to reorder the vector of ordered average ranks.

Abstract: Energy normalization in a speech recognition system is achieved by adaptively tracking the high, mid, and low energy envelopes, wherein the adaptive high energy tracking value adapts with weighting enhanced for high energies, and the adaptive low energy tracking value adapts with weighting enhanced for low energies. A tracking method is also provided for discriminating waveform segments as being one of “speech” or “silence”, and a measure of the signal to noise ratio and absolute noise floor are used as feedback means to achieve optimal speech recognition accuracy.

Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled submicron-wide emitter. In one embodiment, the emitter is contacted by a self-aligned conductive sidewall linked up to a horizontal conductive link. The extrinsic base, embedded within the collector, is recessed below and laterally spaced from the emitter by an insulator layer formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In a third embodiment, the emitter is ring shaped. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area.A novel process of forming vertical (e.g.

Abstract: A novel vertical bipolar device endowed with a lithography-independent tightly controlled sub-micron-wide emitter. In one embodiment, the emitter is contacted by a self-aligned conductive sidewall linked up to a horizontal conductive link. The extrinsic base, embedded within the collector, is recessed below and laterally spaced from the emitter by an insulator layer formed on the emitter sidewall. Transistor action is confined to the small emitter within the intrinsic base, the latter being contiguous with the extrinsic base. The base is contacted by means of a conductive self-aligned silicide formed on the extrinsic base. In a second embodiment, the emitter is of a desired shape with a correspondingly shaped contacting sidewall and pad integral structure. In a third embodiment, the emitter is ring shaped. In all embodiments, electrical contact to emitter is established at a distance laterally away from the transistor action area.