Abstract: A computer system is provided that includes a microprocessor core having an ICE interrupt line to support an in-circuit emulation mode of the computer system. An interrupt control unit coupled to the ICE interrupt line of the microprocessor core, controls a memory control unit in accordance with assertions of an external "debug" interrupt signal and an external SMM (system management mode) interrupt signal. During normal operation, the microprocessor core executes code out of a "normal" memory region of a system memory coupled to the memory control unit. If the debug interrupt signal is asserted while the microprocessor core is operating in normal mode, the interrupt control unit responsively asserts the ICE interrupt signal to the microprocessor core, causing the microprocessor core to read an ICE vector from the system memory and to thereafter execute ICE code.

Abstract: A processing unit is provided that generates an address signal which specifies data on a per-byte basis and that further generates a set of byte enable signals which specify enabled bytes relative to the addressed byte. Both the byte enable signals and the address signal are provided to a memory control unit. The processing unit can thereby generate a single memory access to a misaligned memory address, while still specifying a variable number of enabled bytes. A control input provided to the processing unit controls whether a bus control unit of the processing unit generates single cycle memory accesses to misaligned addresses or two-cycle memory accesses to misaligned addresses. For memory accesses to static RAM, the memory control unit may deassert the control signal such that the processing unit generates two-cycle accesses on misaligned addresses.

Abstract: A configuration register enables built-in testing logic during testing operations, and disables the testing logic during non-testing operations. When enabled, the testing logic is in a normal state, and when disabled the testing logic is in a low power state. The configuration register generates a control signal to the testing logic, the control signal being is responsive to signals received at a key input and a reset input of the configuration register. When the reset input of the configuration register is triggered, the control signal drives the testing logic to the low power state. When a signal matching a predetermined data pattern is applied to the key input, the control signal drives the testing logic to the normal state.