Patents by Inventor Michael D. Powell
Michael D. Powell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118942Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.Type: ApplicationFiled: December 19, 2023Publication date: April 11, 2024Inventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
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Patent number: 11853809Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.Type: GrantFiled: July 5, 2022Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
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Publication number: 20220334887Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.Type: ApplicationFiled: July 5, 2022Publication date: October 20, 2022Inventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
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Patent number: 11413320Abstract: The present application relates to a compositions and methods comprising or expressing a MOMO30 protein derived from Momordica balsamina. The MOMO30 protein is about 30 kDa in size, is stable after being autoclaved at 120° C. for 30 min, resists proteolytic cleavage by trypsin, exhibits mannose-sensitive binding HIV gp120, exhibits hemagglutinin and chitinase activity, is capable of activating and stimulating T cell proliferation, is capable of preventing infection by HIV-1 or alleviating symptoms in an HIV-1 infected patients and comprises the amino acid sequence of SEQ ID NO: 1. The MOMO30 protein and/or a nucleic acid encoding the same may be used in methods for preventing or treating viral infections by HIV and other enveloped viruses.Type: GrantFiled: December 18, 2019Date of Patent: August 16, 2022Assignee: MOREHOUSE SCHOOL OF MEDICINEInventors: Michael D. Powell, Erick Vidjin′ Agnih Gbodossou
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Patent number: 11409577Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.Type: GrantFiled: February 10, 2021Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
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Publication number: 20210263782Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.Type: ApplicationFiled: February 10, 2021Publication date: August 26, 2021Applicant: Intel CorporationInventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
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Patent number: 10922143Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.Type: GrantFiled: August 21, 2018Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
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Publication number: 20200197469Abstract: The present application relates to a compositions and methods comprising or expressing a MOMO30 protein derived from Momordica balsamina. The MOMO30 protein is about 30 kDa in size, is stable after being autoclaved at 120° C. for 30 min, resists proteolytic cleavage by trypsin, exhibits mannose-sensitive binding HIV gp120, exhibits hemagglutinin and chitinase activity, is capable of activating and stimulating T cell proliferation, is capable of preventing infection by HIV-1 or alleviating symptoms in an HIV-1 infected patients and comprises the amino acid sequence of SEQ ID NO: 1. The MOMO30 protein and/or a nucleic acid encoding the same may be used in methods for preventing or treating viral infections by HIV and other enveloped viruses.Type: ApplicationFiled: December 18, 2019Publication date: June 25, 2020Inventors: Michael D. POWELL, Erick Vidjin' Agnih Gbodossou
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Patent number: 10503542Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).Type: GrantFiled: July 30, 2018Date of Patent: December 10, 2019Assignee: INTEL CORPORATIONInventors: Guy Therien, Guy Sotomayor, Arijit Biswas, Michael D. Powell, Eric J. Dehaemer
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Publication number: 20190065242Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).Type: ApplicationFiled: July 30, 2018Publication date: February 28, 2019Applicant: INTEL CORPORATIONInventors: Guy Therien, Guy Sotomayor, Arijit Biswas, Michael D. Powell, Eric J. Dehaemer
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Publication number: 20180357110Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.Type: ApplicationFiled: August 21, 2018Publication date: December 13, 2018Inventors: GUY M. THERIEN, MICHAEL D. POWELL, VENKATESH RAMANI, ARIJIT BISWAS, GUY G. SOTOMAYOR
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Patent number: 10073718Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.Type: GrantFiled: January 15, 2016Date of Patent: September 11, 2018Assignee: Intel CorporationInventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
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Patent number: 10037227Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).Type: GrantFiled: December 17, 2015Date of Patent: July 31, 2018Assignee: INTEL CORPORATIONInventors: Guy Therien, Guy Sotomayor, Arijit Biswas, Michael D. Powell, Eric J. Dehaemer
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Publication number: 20170206118Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.Type: ApplicationFiled: January 15, 2016Publication date: July 20, 2017Inventors: Guy M. THERIEN, Michael D. POWELL, Venkatesh RAMANI, Arijit BISWAS, Guy G. SOTOMAYOR
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Publication number: 20170177407Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).Type: ApplicationFiled: December 17, 2015Publication date: June 22, 2017Applicant: INTEL CORPORATIONInventors: Guy Therien, Guy Sotomayor, Arijit Biswas, Michael D. Powell, Eric J. Dehaemer
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Patent number: 9442559Abstract: A disclosed method includes accessing characterization data indicating first and second sets of performance characteristics for first and second processing cores of a processor; determining, based on a performance objective and the characterization data, a first power state for the first processing core and a second power state for the second processing core; and applying the first power performance objective to the first processing core and the second power performance objective to the second processing core.Type: GrantFiled: March 14, 2013Date of Patent: September 13, 2016Assignee: Intel CorporationInventors: Arijit Biswas, Michael D. Powell
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Patent number: 8914672Abstract: An apparatus and method is described herein for replacing faulty core components. General purpose hardware is provided to replace core pipeline components, such as execution units. In the embodiment of execution unit replacement, a proxy unit is provided, such that mapping logic is able to map instruction/operations, which correspond to faulty execution units, to the proxy unit. As a result, the proxy unit is able to receive the operations, send them to general purpose hardware for execution, and subsequently write-back the execution results to a register file; it essentially replaces the defective execution unit allowing a processor with defective units to be sold or continue operation.Type: GrantFiled: December 28, 2009Date of Patent: December 16, 2014Assignee: Intel CorporationInventors: Steven E. Raasch, Michael D. Powell, Shubhendu S. Mukherjee, Arijit Biswas
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Publication number: 20140281610Abstract: A disclosed method includes accessing characterization data indicating first and second sets of performance characteristics for first and second processing cores of a processor; determining, based on a performance objective and the characterization data, a first power state for the first processing core and a second power state for the second processing core; and applying the first power performance objective to the first processing core and the second power performance objective to the second processing core.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: Intel CorporationInventors: Arijit Biswas, Michael D. Powell
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Publication number: 20130144912Abstract: A method and apparatus effectuates bilateral commerce in ideas. An originator and user-driven on-line commercial network system is designed to facilitate idea submission, purchase, and licensing, and is easily adapted to business-to-business transfers of innovation as well as consumer-to-business transfers of innovation. The invention allows originators of ideas to communicate nondisclosing synopses of ideas globally to potential users, for users conveniently to search for relevant ideas and for users potentially to bind an originator to a limited duration license granting user the exclusive right to access and consider confidentially the originator's fully disclosed idea. The invention also allows users to communicate confidentially or nonconfidentially unsolved problems or needs globally to potential originators, for originators conveniently to search for relevant unsolved problems or needs, and for originators to submit and communicate confidentially proposed solutions to the soliciting user.Type: ApplicationFiled: January 29, 2013Publication date: June 6, 2013Inventor: Michael D. Powell
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Patent number: 8412637Abstract: A method and apparatus effectuates bilateral commerce in ideas. An originator and user-driven on-line commercial network system is designed to facilitate idea submission, purchase, and licensing, and is easily adapted to business-to-business transfers of innovation as well as consumer-to-business transfers of innovation. The invention allows originators of ideas to communicate nondisclosing synopses of ideas globally to potential users, for users conveniently to search for relevant ideas and for users potentially to bind an originator to a limited duration license granting user the exclusive right to access and consider confidentially the originator's fully disclosed idea. The invention also allows users to communicate confidentially or nonconfidentially unsolved problems or needs globally to potential originators, for originators conveniently to search for relevant unsolved problems or needs, and for originators to submit and communicate confidentially proposed solutions to the soliciting user.Type: GrantFiled: April 24, 2006Date of Patent: April 2, 2013Inventor: Michael D. Powell