Patents by Inventor Michael D. Powell

Michael D. Powell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240118942
    Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
    Type: Application
    Filed: December 19, 2023
    Publication date: April 11, 2024
    Inventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
  • Patent number: 11853809
    Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
    Type: Grant
    Filed: July 5, 2022
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
  • Publication number: 20220334887
    Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Inventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
  • Patent number: 11413320
    Abstract: The present application relates to a compositions and methods comprising or expressing a MOMO30 protein derived from Momordica balsamina. The MOMO30 protein is about 30 kDa in size, is stable after being autoclaved at 120° C. for 30 min, resists proteolytic cleavage by trypsin, exhibits mannose-sensitive binding HIV gp120, exhibits hemagglutinin and chitinase activity, is capable of activating and stimulating T cell proliferation, is capable of preventing infection by HIV-1 or alleviating symptoms in an HIV-1 infected patients and comprises the amino acid sequence of SEQ ID NO: 1. The MOMO30 protein and/or a nucleic acid encoding the same may be used in methods for preventing or treating viral infections by HIV and other enveloped viruses.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 16, 2022
    Assignee: MOREHOUSE SCHOOL OF MEDICINE
    Inventors: Michael D. Powell, Erick Vidjin′ Agnih Gbodossou
  • Patent number: 11409577
    Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
  • Publication number: 20210263782
    Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
    Type: Application
    Filed: February 10, 2021
    Publication date: August 26, 2021
    Applicant: Intel Corporation
    Inventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
  • Patent number: 10922143
    Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
  • Publication number: 20200197469
    Abstract: The present application relates to a compositions and methods comprising or expressing a MOMO30 protein derived from Momordica balsamina. The MOMO30 protein is about 30 kDa in size, is stable after being autoclaved at 120° C. for 30 min, resists proteolytic cleavage by trypsin, exhibits mannose-sensitive binding HIV gp120, exhibits hemagglutinin and chitinase activity, is capable of activating and stimulating T cell proliferation, is capable of preventing infection by HIV-1 or alleviating symptoms in an HIV-1 infected patients and comprises the amino acid sequence of SEQ ID NO: 1. The MOMO30 protein and/or a nucleic acid encoding the same may be used in methods for preventing or treating viral infections by HIV and other enveloped viruses.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 25, 2020
    Inventors: Michael D. POWELL, Erick Vidjin' Agnih Gbodossou
  • Patent number: 10503542
    Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: December 10, 2019
    Assignee: INTEL CORPORATION
    Inventors: Guy Therien, Guy Sotomayor, Arijit Biswas, Michael D. Powell, Eric J. Dehaemer
  • Publication number: 20190065242
    Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).
    Type: Application
    Filed: July 30, 2018
    Publication date: February 28, 2019
    Applicant: INTEL CORPORATION
    Inventors: Guy Therien, Guy Sotomayor, Arijit Biswas, Michael D. Powell, Eric J. Dehaemer
  • Publication number: 20180357110
    Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 13, 2018
    Inventors: GUY M. THERIEN, MICHAEL D. POWELL, VENKATESH RAMANI, ARIJIT BISWAS, GUY G. SOTOMAYOR
  • Patent number: 10073718
    Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Guy M. Therien, Michael D. Powell, Venkatesh Ramani, Arijit Biswas, Guy G. Sotomayor
  • Patent number: 10037227
    Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: July 31, 2018
    Assignee: INTEL CORPORATION
    Inventors: Guy Therien, Guy Sotomayor, Arijit Biswas, Michael D. Powell, Eric J. Dehaemer
  • Publication number: 20170206118
    Abstract: Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Guy M. THERIEN, Michael D. POWELL, Venkatesh RAMANI, Arijit BISWAS, Guy G. SOTOMAYOR
  • Publication number: 20170177407
    Abstract: Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).
    Type: Application
    Filed: December 17, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Guy Therien, Guy Sotomayor, Arijit Biswas, Michael D. Powell, Eric J. Dehaemer
  • Patent number: 9442559
    Abstract: A disclosed method includes accessing characterization data indicating first and second sets of performance characteristics for first and second processing cores of a processor; determining, based on a performance objective and the characterization data, a first power state for the first processing core and a second power state for the second processing core; and applying the first power performance objective to the first processing core and the second power performance objective to the second processing core.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Arijit Biswas, Michael D. Powell
  • Patent number: 8914672
    Abstract: An apparatus and method is described herein for replacing faulty core components. General purpose hardware is provided to replace core pipeline components, such as execution units. In the embodiment of execution unit replacement, a proxy unit is provided, such that mapping logic is able to map instruction/operations, which correspond to faulty execution units, to the proxy unit. As a result, the proxy unit is able to receive the operations, send them to general purpose hardware for execution, and subsequently write-back the execution results to a register file; it essentially replaces the defective execution unit allowing a processor with defective units to be sold or continue operation.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Steven E. Raasch, Michael D. Powell, Shubhendu S. Mukherjee, Arijit Biswas
  • Publication number: 20140281610
    Abstract: A disclosed method includes accessing characterization data indicating first and second sets of performance characteristics for first and second processing cores of a processor; determining, based on a performance objective and the characterization data, a first power state for the first processing core and a second power state for the second processing core; and applying the first power performance objective to the first processing core and the second power performance objective to the second processing core.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Intel Corporation
    Inventors: Arijit Biswas, Michael D. Powell
  • Publication number: 20130144912
    Abstract: A method and apparatus effectuates bilateral commerce in ideas. An originator and user-driven on-line commercial network system is designed to facilitate idea submission, purchase, and licensing, and is easily adapted to business-to-business transfers of innovation as well as consumer-to-business transfers of innovation. The invention allows originators of ideas to communicate nondisclosing synopses of ideas globally to potential users, for users conveniently to search for relevant ideas and for users potentially to bind an originator to a limited duration license granting user the exclusive right to access and consider confidentially the originator's fully disclosed idea. The invention also allows users to communicate confidentially or nonconfidentially unsolved problems or needs globally to potential originators, for originators conveniently to search for relevant unsolved problems or needs, and for originators to submit and communicate confidentially proposed solutions to the soliciting user.
    Type: Application
    Filed: January 29, 2013
    Publication date: June 6, 2013
    Inventor: Michael D. Powell
  • Patent number: 8412637
    Abstract: A method and apparatus effectuates bilateral commerce in ideas. An originator and user-driven on-line commercial network system is designed to facilitate idea submission, purchase, and licensing, and is easily adapted to business-to-business transfers of innovation as well as consumer-to-business transfers of innovation. The invention allows originators of ideas to communicate nondisclosing synopses of ideas globally to potential users, for users conveniently to search for relevant ideas and for users potentially to bind an originator to a limited duration license granting user the exclusive right to access and consider confidentially the originator's fully disclosed idea. The invention also allows users to communicate confidentially or nonconfidentially unsolved problems or needs globally to potential originators, for originators conveniently to search for relevant unsolved problems or needs, and for originators to submit and communicate confidentially proposed solutions to the soliciting user.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: April 2, 2013
    Inventor: Michael D. Powell