Patents by Inventor Michael D. Rosotker

Michael D. Rosotker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of increasing the layout efficiency of dies on a wafer, and increasing the ratio of I/O area to active area per die
    Patent number: 5341024
    Abstract: Certain non-square dies, such as triangular dies, greatly elongated rectangular dies, parallelogram dies, trapezoidal, and the like, are able to be laid out in the area of a circular semiconductor wafer more "efficiently" than square dies. Further, a peripheral area of these certain non-square dies is advantageously increased relative to the area contained within the peripheral area, to accommodate increased I/O connections to the active elements of the die.
    Type: Grant
    Filed: November 18, 1992
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rosotker
  • Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
    Patent number: 5340772
    Abstract: Certain non-square dies, such as triangular dies, greatly elongated rectangular dies, parallelogram dies, trapezoidal, and the like, are able to be laid out in the area of a circular semiconductor wafer more "efficiently" than square dies. Further, a peripheral area of these certain non-square dies is advantageously increased relative to the area contained within the peripheral area, to accommodate increased I/O connections to the active elements of the die.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rosotker
  • Semiconductor packaging technique yielding increased inner lead count for a given die-receiving area
    Patent number: 5329157
    Abstract: A greater lead count for a given die area can be achieved with "certain non-square" geometries formed by the inner ends of conductive lines. These include various triangular configurations, as well as "greatly elongated" rectangular, parallelogram and trapezoidal configurations. The conductive lines may be leads of a lead frame, leads on a tape-based package, or traces on ceramic or PCB-substrate packages. The package body may be formed to have a shape similar to that of the die receiving area, and may also be provided with external pins, ball bumps or leads. A number of these "certain non-square" packages may be assembled in an electronic system on a mother board. Unpackaged "certain non-square" dies may be connected to the ends of traces on a substrate, and encapsulated to form a multi-chip module.
    Type: Grant
    Filed: August 21, 1992
    Date of Patent: July 12, 1994
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rosotker