Patents by Inventor Michael D. Ruehle
Michael D. Ruehle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8219508Abstract: Systems and methods for compressing state machine instructions are disclosed herein. In one embodiment, the method comprises associating input characters associated with states to respective indices, where each index comprises information indicative of a particular transition instruction.Type: GrantFiled: July 2, 2008Date of Patent: July 10, 2012Assignee: LSI CorporationInventors: Robert James McMillen, Michael D. Ruehle
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Patent number: 8190738Abstract: A system and method for hardware processing of regular expressions is disclosed. A register bank is loaded with state information associated with one or more states of a state machine. State information such as transitions and spin counts are updated as characters of an input data stream are processed. A crossbar is used to interconnect the states stored in the register bank.Type: GrantFiled: January 29, 2011Date of Patent: May 29, 2012Assignee: LSI CorporationInventor: Michael D. Ruehle
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Publication number: 20110125695Abstract: A system and method for hardware processing of regular expressions is disclosed. A register bank is loaded with state information associated with one or more states of a state machine. State information such as transitions and spin counts are updated as characters of an input data stream are processed. A crossbar is used to interconnect the states stored in the register bank.Type: ApplicationFiled: January 29, 2011Publication date: May 26, 2011Inventor: Michael D. Ruehle
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Patent number: 7899904Abstract: A system and method for hardware processing of regular expressions is disclosed. A register bank is loaded with state information associated with one or more states of a state machine. State information such as transitions and spin counts are updated as characters of an input data stream are processed. A crossbar is used to interconnect the states stored in the register bank.Type: GrantFiled: April 30, 2008Date of Patent: March 1, 2011Assignee: LSI CorporationInventor: Michael D. Ruehle
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Patent number: 7788206Abstract: Compressing state transition instructions may achieve a reduction in the binary instruction footprint of a state machine. In certain embodiments, the compressed state transition instructions are used by state machine engines that use one or more caches in order to increase the speed at which the state machine engine can execute a state machine. In addition to reducing the instruction footprint, the use of compressed state transition instructions as discussed herein may also increase the cache hit rate of a cache-based state machine engine, resulting in an increase in performance.Type: GrantFiled: April 30, 2008Date of Patent: August 31, 2010Assignee: LSI CorporationInventors: Robert James McMillen, Michael D. Ruehle
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Patent number: 7564379Abstract: Several code detectors in parallel simultaneously examine varying overlapping segments of a data stream containing variable length codes, referred to as a data window. The data window segments directly address memory structures within each of the code detectors without any previous logic stages. Each code detector is responsible for a range of code lengths, and ignores data window bits that are not relevant to its code length range. Each code detector outputs a possible result to a layer of logic that selects the possible result of the single code detector which contains result data corresponding to a variable length code in the data window.Type: GrantFiled: October 16, 2007Date of Patent: July 21, 2009Assignee: LSI CorporationInventor: Michael D. Ruehle
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Publication number: 20090063825Abstract: Systems and methods for compressing state machine instructions are disclosed herein. In one embodiment, the method comprises associating input characters associated with states to respective indices, where each index comprises information indicative of a particular transition instruction.Type: ApplicationFiled: July 2, 2008Publication date: March 5, 2009Inventors: Robert James McMillen, Michael D. Ruehle
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Publication number: 20080270764Abstract: Compressing state transition instructions may achieve a reduction in the binary instruction footprint of a state machine. In certain embodiments, the compressed state transition instructions are used by state machine engines that use one or more caches in order to increase the speed at which the state machine engine can execute a state machine. In addition to reducing the instruction footprint, the use of compressed state transition instructions as discussed herein may also increase the cache hit rate of a cache-based state machine engine, resulting in an increase in performance.Type: ApplicationFiled: April 30, 2008Publication date: October 30, 2008Inventors: Robert James McMillen, Michael D. Ruehle
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Publication number: 20080270342Abstract: A system and method for hardware processing of regular expressions is disclosed. A register bank is loaded with state information associated with one or more states of a state machine. State information such as transitions and spin counts are updated as characters of an input data stream are processed. A crossbar is used to interconnect the states stored in the register bank.Type: ApplicationFiled: April 30, 2008Publication date: October 30, 2008Applicant: Tarari, Inc.Inventor: Michael D. Ruehle
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Publication number: 20080144728Abstract: Several code detectors in parallel simultaneously examine varying overlapping segments of a data stream containing variable length codes, referred to as a data window. The data window segments directly address memory structures within each of the code detectors without any previous logic stages. Each code detector is responsible for a range of code lengths, and ignores data window bits that are not relevant to its code length range. Each code detector outputs a possible result to a layer of logic that selects the possible result of the single code detector which contains result data corresponding to a variable length code in the data window.Type: ApplicationFiled: October 16, 2007Publication date: June 19, 2008Applicant: Tarari, Inc.Inventor: Michael D. Ruehle
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Patent number: 7283591Abstract: Several code detectors in parallel simultaneously examine varying overlapping segments of a data stream containing variable length codes, referred to as a data window. The data window segments directly address memory structures within each of the code detectors without any previous logic stages. Each code detector is responsible for a range of code lengths, and ignores data window bits that are not relevant to its code length range. Each code detector outputs a possible result to a layer of logic that selects the possible result of the single code detector which contains result data corresponding to a variable length code in the data window.Type: GrantFiled: August 7, 2003Date of Patent: October 16, 2007Assignee: Tarari, Inc.Inventor: Michael D. Ruehle
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Patent number: 7177301Abstract: A method of constructing a permuting network. A configuration for layers of a permuting network is selected based on a set of integer factors of N, the number of signals to be permuted, and on pre-selected types of switches. The permuting network is constructed in layers by using the pre-selected types of switches based on the selected configuration.Type: GrantFiled: December 27, 2001Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: Michael D. Ruehle
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Patent number: 6922717Abstract: A method and apparatus for performing modular multiplication is disclosed. An apparatus in accordance with one embodiment of the present invention includes a modular multiplier including a plurality of independent computation channels, where the plurality of independent computation channels includes a first computation channel and a second computation channel, and a coupling device interposed between the first computation channel and the second computation channel to receive a control signal and to couple the first computation channel to the second computation channel in response to a receipt of the control signal.Type: GrantFiled: September 28, 2001Date of Patent: July 26, 2005Assignee: Intel CorporationInventor: Michael D. Ruehle
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Publication number: 20040190635Abstract: Several code detectors in parallel simultaneously examine varying overlapping segments of a data stream containing variable length codes, referred to as a data window. The data window segments directly address memory structures within each of the code detectors without any previous logic stages. Each code detector is responsible for a range of code lengths, and ignores data window bits that are not relevant to its code length range. Each code detector outputs a possible result to a layer of logic that selects the possible result of the single code detector which contains result data corresponding to a variable length code in the data window.Type: ApplicationFiled: August 7, 2003Publication date: September 30, 2004Inventor: Michael D. Ruehle
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Patent number: 6748412Abstract: Processing exponents with a square-and-multiply technique that uses a flexible number of bits in the multiply stages. Multiple bits of the exponent can be handled in a single multiply operation, thus reducing the total number of multiply operations required to raise a number to a specified power. By examining prior and subsequent bits in the exponent in addition to the current bit, the quantity of bits that are handled in a particular multiply operation can be adjusted to the particular pattern of 1's and 0's in the exponent.Type: GrantFiled: September 26, 2001Date of Patent: June 8, 2004Assignee: Intel CorporationInventor: Michael D. Ruehle
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Patent number: 6732133Abstract: A linear systolic array Montgomery multiplier circuit that concurrently processes two separate Montgomery multiplications on alternate clock cycles, without a requirement to have any common parameters between the two multiplications. Multiples of two different parameters are stored in storage elements for each multiplication. Two sets of these multiples, one set for each of the two multiplications, are stored in separate storage banks and accessed on alternate clock cycles by each processing element in the array. Two sequences of control codes for the two multiplications are interleaved as they are fed into a first processing element.Type: GrantFiled: September 28, 2001Date of Patent: May 4, 2004Assignee: Intel CorporationInventor: Michael D. Ruehle
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Patent number: 6625631Abstract: A Montgomery multiplier circuit with a chain of processing elements uses less circuit logic in each processing element by propagating an initial parameter through registers used for other purposes. An accumulation register in each processing element is used to propagate the initial parameter through the chain. In one embodiment the initial parameter is first propagated through address registers until it reaches the end of the chain, and is then looped back through the accumulation registers in the reverse direction. In one embodiment, multiples of at least one parameter used in a Montgomery multiplication are pre-calculated in the processing elements of the Montgomery multiplier using the same logic elements used in performing the Montgomery multiplication.Type: GrantFiled: September 28, 2001Date of Patent: September 23, 2003Assignee: Intel CorporationInventor: Michael D. Ruehle
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Publication number: 20030123439Abstract: A method of constructing a permuting network. A configuration for layers of a permuting network is selected based on a set of integer factors of N, the number of signals to be permuted, and on pre-selected types of switches. The permuting network is constructed in layers by using the pre-selected types of switches based on the selected configuration.Type: ApplicationFiled: December 27, 2001Publication date: July 3, 2003Inventor: Michael D. Ruehle
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Publication number: 20030093453Abstract: Processing exponents with a square-and-multiply technique that uses a flexible number of bits in the multiply stages. Multiple bits of the exponent can be handled in a single multiply operation, thus reducing the total number of multiply operations required to raise a number to a specified power. By examining prior and subsequent bits in the exponent in addition to the current bit, the quantity of bits that are handled in a particular multiply operation can be adjusted to the particular pattern of 1's and 0's in the exponent.Type: ApplicationFiled: September 26, 2001Publication date: May 15, 2003Inventor: Michael D. Ruehle
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Publication number: 20030065694Abstract: A linear systolic array Montgomery multiplier circuit that concurrently processes two separate Montgomery multiplications on alternate clock cycles, without a requirement to have any common parameters between the two multiplications. Multiples of two different parameters are stored in storage elements for each multiplication. Two sets of these multiples, one set for each of the two multiplications, are stored in separate storage banks and accessed on alternate clock cycles by each processing element in the array. Two sequences of control codes for the two multiplications are interleaved as they are fed into a first processing element.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventor: Michael D. Ruehle