Abstract: In an embodiment, dynamically-generated code may be supported in the system by ensuring that the code either remains executing within a predefined region of memory or exits to one of a set of valid exit addresses. Software embodiments are described in which the dynamically-generated code is scanned prior to permitting execution of the dynamically-generated code to ensure that various criteria are met including exclusion of certain disallowed instructions and control of branch target addresses. Hardware embodiments are described in which the dynamically-generated code is permitted to executed but is monitored to ensure that the execution criteria are met.

Abstract: An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

Abstract: In an embodiment, dynamically-generated code may be supported in the system by ensuring that the code either remains executing within a predefined region of memory or exits to one of a set of valid exit addresses. Software embodiments are described in which the dynamically-generated code is scanned prior to permitting execution of the dynamically-generated code to ensure that various criteria are met including exclusion of certain disallowed instructions and control of branch target addresses. Hardware embodiments are described in which the dynamically-generated code is permitted to executed but is monitored to ensure that the execution criteria are met.

Abstract: In an embodiment, dynamically-generated code may be supported in the system by ensuring that the code either remains executing within a predefined region of memory or exits to one of a set of valid exit addresses. Software embodiments are described in which the dynamically-generated code is scanned prior to permitting execution of the dynamically-generated code to ensure that various criteria are met including exclusion of certain disallowed instructions and control of branch target addresses. Hardware embodiments are described in which the dynamically-generated code is permitted to executed but is monitored to ensure that the execution criteria are met.

Abstract: An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

Abstract: A communication system including a media server through which communication packets are exchanged for recording and monitoring purposes is disclosed. A tap is associated with each communication endpoint allowing for cradle to grave recording of communications despite their subsequent routing or branching. An incoming communication is routed to a first tap and upon selection of a receiving party; the first tap is routed to a second tap which forwards communication packets on to the receiving party. The taps may be used to forward communication packets to any number of other taps or destinations, such as a recording device, monitoring user, or other user in the form of a conference.

Abstract: A system and method are presented for voicemail acceleration. A voicemail acceleration system, which functions to accelerate the experience of a user, is associated with at least one user device. A user may initiate an interaction with another user, wherein the device associated with the voicemail acceleration system detects that the interaction is being sent to voicemail through contact analysis. A pre-established message and/or a number of options may be presented to the user initiating the interaction, wherein the user may choose an option or elect to automatically leave a message and end the interaction on their end. The voicemail acceleration system provides the retrieved message to the other user and finishes the interaction.

Abstract: A system and method are presented for voicemail acceleration. A voicemail acceleration system, which functions to accelerate the experience of a user, is associated with at least one user device. A user may initiate an interaction with another user, wherein the device associated with the voicemail acceleration system detects that the interaction is being sent to voicemail through contact analysis. A pre-established message and/or a number of options may be presented to the user initiating the interaction, wherein the user may choose an option or elect to automatically leave a message and end the interaction on their end. The voicemail acceleration system provides the retrieved message to the other user and finishes the interaction.

Abstract: A system and method are presented for voicemail acceleration. A voicemail acceleration system, which functions to accelerate the experience of a user, is associated with at least one user device. A user may initiate an interaction with another user, wherein the device associated with the voicemail acceleration system detects that the interaction is being sent to voicemail through contact analysis. A pre-established message and/or a number of options may be presented to the user initiating the interaction, wherein the user may choose an option or elect to automatically leave a message and end the interaction on their end. The voicemail acceleration system provides the retrieved message to the other user and finishes the interaction.

Abstract: A communication system including a media server through which communication packets are exchanged for recording and monitoring purposes is disclosed. A tap is associated with each communication endpoint allowing for cradle to grave recording of communications despite their subsequent routing or branching. An incoming communication is routed to a first tap and upon selection of a receiving party; the first tap is routed to a second tap which forwards communication packets on to the receiving party. The taps may be used to forward communication packets to any number of other taps or destinations, such as a recording device, monitoring user, or other user in the form of a conference.

Abstract: A communication system including a media server through which communication packets are exchanged for recording and monitoring purposes is disclosed. A tap is associated with each communication endpoint allowing for cradle to grave recording of communications despite their subsequent routing or branching. An incoming communication is routed to a first tap and upon selection of a receiving party; the first tap is routed to a second tap which forwards communication packets on to the receiving party. The taps may be used to forward communication packets to any number of other taps or destinations, such as a recording device, monitoring user, or other user in the form of a conference.

Abstract: For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug related instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread, wherein processing the debug event comprises causing a halting operation related to the processor.

Abstract: A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. A decorated storage notify (DSN) transaction includes an indication of an instruction operation, an address associated with the instruction operation, and a decoration value (i.e. a command to the target device to perform a function in addition to a store or a load). The transaction on the system interconnect includes an address phase and no data phase, thereby improving system bandwidth. In one form the target device (e.g. a memory with functionality in addition to storage functionality) performs a read-modify-write operation using information at a storage location of the target device.

Abstract: A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.

Abstract: A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second indicator depending on whether the coherency state value represents a cumulative coherency state for a plurality of caches of the processor. The first indicator and the second indicator identify the coherency state value as representing a cumulative coherency state or a potentially non-cumulative coherency state, respectively. If the second indicator is provided, a transaction management module determines whether to request the cumulative coherency state for the coherency granule in response to receiving the second indicator. The transaction management module then provides an indicator of the request for the cumulative coherency state to the processor in response to determining to request the cumulative coherency state.

Abstract: A plurality of new snoop transaction types are described. Some include address information in the requests, and others include cache entry information in the requests. Some responses include tag address information, and some do not. Some provide tag address content on the data bus lines during the data portion of the transaction. These new snoop transaction types are very helpful during debug of a data processing system.

Abstract: A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.

Abstract: A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. The transactions include an indication of an instruction operation, an address associated with the instruction operation, a decoration value (i.e. a command to the target device to perform a function in addition to a primary function of the executed instruction), and access permissions associated with the address. The target device (e.g. a memory with functionality in addition to storage functionality) determines whether a decoration operation specified by the decoration value is permissible based on the received access permissions. The target device performs the decoration operation if appropriate permissions exist.

Abstract: A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.