Patents by Inventor Michael D. Sugino

Michael D. Sugino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4591890
    Abstract: Radiation hard, N-channel MOS devices comprising active regions surrounded by field oxide protected by an underlying region of heavily doped p-type material. The guard region is doped heavily enough to provide field inversion voltages in the range of 50 V to 60 V prior to irradiation. The guard region is separated from the source and drain regions to provide acceptably high breakdown voltages. The devices are produced with minor variations to well known, high density local oxidation of silicon-type processes.
    Type: Grant
    Filed: December 20, 1982
    Date of Patent: May 27, 1986
    Assignee: Motorola Inc.
    Inventors: Clarence A. Lund, Michael D. Sugino
  • Patent number: 4503451
    Abstract: In a channel formed in one surface of a semiconductor substrate having a first conductivity, e.g. N type, a layer of material having a second conductivity type, e.g. P type boron, and a layer of relatively low resistance material such as Tungsten in contact with the first layer but insulated from the substrate. Second conductivity type tubs and the like can be formed adjacent the bus and in direct contact therewith through the first layer.
    Type: Grant
    Filed: July 30, 1982
    Date of Patent: March 5, 1985
    Assignee: Motorola, Inc.
    Inventors: Clarence A. Lund, Michael D. Sugino
  • Patent number: 4319395
    Abstract: A self-aligned MOS transistor having improved operating characteristics and higher packing density and a method for fabricating the device. Resistance of the gate electrode is reduced substantially by forming the electrode of a metal silicide. Resistance of the source and drain regions is likewise reduced substantially by forming a metal silicide in the doped junction region which allows those regions to be smaller and to require less area. The silicided source and drain regions are self-aligned with and closely spaced to the silicided gate electrode. This is provided by a process which utilizes and makes possible an undercut etching of a polycrystalline silicon gate electrode.
    Type: Grant
    Filed: June 28, 1979
    Date of Patent: March 16, 1982
    Assignee: Motorola, Inc.
    Inventors: Clarence A. Lund, Edward W. Barron, Howard E. Holstin, Michael D. Sugino