Patents by Inventor Michael D. Upton
Michael D. Upton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9785436Abstract: An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations.Type: GrantFiled: September 28, 2012Date of Patent: October 10, 2017Assignee: INTEL CORPORATIONInventors: Edward T. Grochowski, Dennis R. Bradford, George Z. Chrysos, Andrew T. Forsyth, Michael D. Upton, Lisa K. Wu
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Publication number: 20170031729Abstract: Disclosed herein is a generational thread scheduler. One embodiment may be used with processor multithreading logic to execute threads of executable instructions, and a shared resource to be allocated fairly among the threads of executable instructions contending for access to the shared resource. Generational thread scheduling logic may allocate the shared resource efficiently and fairly by granting a first requesting thread access to the shared resource allocating a reservation for the shared resource to each other requesting thread of the executing threads and then blocking the first thread from re-requesting the shared resource until every other thread that has been allocated a reservation, has been granted access to the shared resource. Generation tracking state may be cleared when each requesting thread of the generation that was allocated a reservation has had their request satisfied.Type: ApplicationFiled: October 11, 2016Publication date: February 2, 2017Inventors: Edward T. Grochowski, Michael D. Upton, George Z. Chrysos, Chunhui Zhang, Mohammed L. Al-Aqrabawi
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Patent number: 9465670Abstract: Disclosed herein is a generational thread scheduler. One embodiment may be used with processor multithreading logic to execute threads of executable instructions, and a shared resource to be allocated fairly among the threads of executable instructions contending for access to the shared resource. Generational thread scheduling logic may allocate the shared resource efficiently and fairly by granting a first requesting thread access to the shared resource allocating a reservation for the shared resource to each other requesting thread of the executing threads and then blocking the first thread from re-requesting the shared resource until every other thread that has been allocated a reservation, has been granted access to the shared resource. Generation tracking state may be cleared when each requesting thread of the generation that was allocated a reservation has had their request satisfied.Type: GrantFiled: December 16, 2011Date of Patent: October 11, 2016Assignee: Intel CorporationInventors: Edward T. Grochowski, Michael D. Upton, George Z. Chrysos, Chunhui C. Zhang, Mohammed L. Al-Aqrabawi
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Patent number: 8850165Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.Type: GrantFiled: June 7, 2011Date of Patent: September 30, 2014Assignee: Intel CorporationInventors: David W. Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, David J. Sager
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Publication number: 20140095831Abstract: An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Edward T. Grochowski, Dennis R. Bradford, George Z. Chrysos, Andrew T. Forsyth, Michael D. Upton, Lisa K. Wu
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Publication number: 20130160020Abstract: Disclosed herein is a generational thread scheduler. One embodiment may be used with processor multithreading logic to execute threads of executable instructions, and a shared resource to be allocated fairly among the threads of executable instructions contending for access to the shared resource. Generational thread scheduling logic may allocate the shared resource efficiently and fairly by granting a first requesting thread access to the shared resource allocating a reservation for the shared resource to each other requesting thread of the executing threads and then blocking the first thread from re-requesting the shared resource until every other thread that has been allocated a reservation, has been granted access to the shared resource. Generation tracking state may be cleared when each requesting thread of the generation that was allocated a reservation has had their request satisfied.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Inventors: Edward T. Grochowski, Michael D. Upton, George Z. Chrysos, Chunhui C. Zhang, Mohammed L. Al-Aqrabawi
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Publication number: 20120042151Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.Type: ApplicationFiled: September 10, 2010Publication date: February 16, 2012Inventors: David J. Sager, Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton
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Publication number: 20110239221Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.Type: ApplicationFiled: June 7, 2011Publication date: September 29, 2011Inventors: David W. Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, David J. Sager
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Patent number: 7987346Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.Type: GrantFiled: January 21, 2011Date of Patent: July 26, 2011Assignee: Intel CorporationInventors: David Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, David J. Sager
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Publication number: 20110113222Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.Type: ApplicationFiled: January 21, 2011Publication date: May 12, 2011Applicant: INTEL CORPORATIONInventors: David W. BURNS, James D. ALLEN, Michael D. UPTON, Darrell D. BOGGS, David J. SAGER
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Patent number: 7877583Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.Type: GrantFiled: November 7, 2008Date of Patent: January 25, 2011Assignee: Intel CorporationInventors: David W. Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, David J. Sager
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Publication number: 20090070562Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.Type: ApplicationFiled: November 7, 2008Publication date: March 12, 2009Applicant: INTEL CORPORATIONInventors: David W. BURNS, James D. ALLEN, Michael D. UPTON, Darrell D. BOGGS, David J. SAGER
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Patent number: 7454600Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.Type: GrantFiled: June 22, 2001Date of Patent: November 18, 2008Assignee: Intel CorporationInventors: David W. Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, David J. Sager
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Patent number: 7085889Abstract: A context identifier is used in a cache memory apparatus. The context identifier may be written into the tag of a cache line or may be written as an addition to the tag of a cache line, during cache write operation. During a cache read operation, the context identifier of as issued instruction may be compared with the context identifier in the cache line's tag. The cache line's data block may be transferred if the context identifiers and the tags match.Type: GrantFiled: March 22, 2002Date of Patent: August 1, 2006Assignee: Intel CorporationInventors: Per Hammarlund, Aravindh Baktha, Michael D Upton, Venkat K. S. Venkatraman
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Patent number: 7010669Abstract: In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.Type: GrantFiled: October 10, 2003Date of Patent: March 7, 2006Assignee: Intel CorporationInventors: David W. Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, Alan B. Kyker
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Patent number: 6735688Abstract: According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.Type: GrantFiled: February 14, 2000Date of Patent: May 11, 2004Assignee: Intel CorporationInventors: Michael D. Upton, David J. Sager, Darrell Boggs, Glenn J. Hinton
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Publication number: 20040078794Abstract: In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.Type: ApplicationFiled: October 10, 2003Publication date: April 22, 2004Inventors: David W. Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, Alan B. Kyker
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Patent number: 6651158Abstract: In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.Type: GrantFiled: June 22, 2001Date of Patent: November 18, 2003Assignee: Intel CorporationInventors: David W. Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, Alan B. Kyker
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Patent number: RE44494Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.Type: GrantFiled: November 24, 2004Date of Patent: September 10, 2013Assignee: Intel CorporationInventors: David J. Sager, Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton
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Patent number: RE45487Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.Type: GrantFiled: March 14, 2013Date of Patent: April 21, 2015Assignee: Intel CorporationInventors: David J. Sager, Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton