Abstract: A signal processing array architecture using a common multiport global memory to interface to a plurality of digital signal processors. The present architecture permits mixing of various types of digital signal processors, commercially available computers, and logic devices. The present signal processing architecture is comprised of a plurality of processing nodes (20) that each comprise a dual processor that is coupled to a local memory by way of a RAM loader bus. An emulated multiport memory is coupled to the dual processor by way of a local bus. A sensor bus is provided for transferring sensor signals from an external sensor to the emulated multiport memory. A global bus is provided that permits communication between each processing node. A bus controller is coupled between the emulated dual port memory and the sensor and global busses for controlling movement of signals to and from the emulated dual port memory.