Abstract: A method of programming a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises allowing current to flow through the data storage element until a predetermined current or voltage is detected. If the current or voltage exceeds a threshold, then the programming is deemed complete.

Abstract: A method of testing the programmability of a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises applying a test voltage across the data storage element. The select transistor is turned on. Finally, a current flow through the data storage element when the test voltage is applied is measured. A test positive signal is indicated if the current flow is greater than a reference.

Abstract: A cell that can be used as a dynamic memory cell for storing data or a field programmable gate array (FPGA) cell for programming is disclosed. The cell includes a capacitor having a first terminal connected to a column bitline and a second terminal connected to a switch control node. A select transistor has a gate connected to the read bitline, a source connected to the switch control node, and a drain connected to a row wordline. The switch control node stores data as a voltage indicative of a one or a zero.

Abstract: A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor. Further, a gate dielectric of the transistor has a higher breakdown voltage near the source connected to the row wordline than its drain.

Abstract: A method of programming a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises allowing current to flow through the data storage element until a predetermined current or voltage is detected. If the current or voltage exceeds a threshold, then the programming is deemed complete.

Abstract: A method of testing the programmability of a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises applying a test voltage across the data storage element. The select transistor is turned on. Finally, a current flow through the data storage element when the test voltage is applied is measured. A test positive signal is indicated if the current flow is greater than a reference.

Abstract: A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor. Further, a gate dielectric of the transistor has a higher breakdown voltage near the source connected to the row wordline than its drain.

Abstract: In a non-volatile memory comprising a region 2 for core memory cells and a peripheral region 4a on a substrate 6, a method for improving electrostatic discharge (ESD) robustness of the non-volatile memory comprises the steps of lightly doping the source and drain regions 18 and 20 of a peripheral transistor 12 in the peripheral region 4a with a first n-type dopant, providing a double diffusion implant mask 10 having an opening over the region 2 for the core memory cells and also an opening 8 over the peripheral region 4a, and performing a double diffusion implantation through the opening 8 over the peripheral region 4a. In an embodiment, the step of performing the double-diffusion implantation comprises the steps of implanting a second n-type dopant comprising phosphorus into the source and drain regions 18 and 20, and implanting a third n-type dopant comprising arsenic into the source and drain regions 18 and 20 subsequent to the step of implanting the second n-type dopant.