Abstract: A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate is then formed over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. In one method, the top substrate contains a conductor pattern that connects to LED electrodes and conductors on the bottom substrate.

Abstract: A metal stack for templating the growth of AlN and ScAlN films is disclosed. The metal stack comprises one, two, or three layers of metal, each of which is compatible with CMOS post-processing. The metal stack provides a template that promotes the growth of highly textured c-axis {002} AlN and ScAlN films. The metal stacks include one or more metal layers with each metal layer having either a hexagonal {002} orientation or a cubic {111} orientation. If the metal stack includes two or more metal layers, the layers can alternate between hexagonal {002} and cubic {111} orientations. The use of ScAlN results in a higher piezoelectric constant compared to that of AlN for ScAlN alloys up to approximately 44% Sc. The disclosed metal stacks resulted in ScAlN films having XRD FWHM values of less than approximately 1.1° while significantly reducing the formation of secondary grains in the ScAlN films.

Abstract: A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate is then formed over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. In one method, the top substrate contains a conductor pattern that connects to LED electrodes and conductors on the bottom substrate.

Abstract: The invention is directed to a device and method to engineer the superconducting transition width by suppressing the phonon populations responsible for the Cooper-pair decoherence below the superconducting transition temperature via phononic bandgap engineering. The device uses phononic crystals to engineer a phononic frequency gap that suppresses the decohering thermal phonon population just below the Cooper-frequency, and thus the normal conduction electron population. For example, such engineering can relax the cooling requirements for a variety of circuits yielding higher operational quality factors for superconducting electronics and interconnects.

Abstract: The invention is directed to a device and method to engineer the superconducting transition width by suppressing the phonon populations responsible for the Cooper-pair decoherence below the superconducting transition temperature via phononic bandgap engineering. The device uses phononic crystals to engineer a phononic frequency gap that suppresses the decohering thermal phonon population just below the Cooper-frequency, and thus the normal conduction electron population. For example, such engineering can relax the cooling requirements for a variety of circuits yielding higher operational quality factors for superconducting electronics and interconnects.

Abstract: A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate is then formed over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. In one method, the top substrate contains a conductor pattern that connects to LED electrodes and conductors on the bottom substrate.

Abstract: A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate is then formed over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. In one method, the top substrate contains a conductor pattern that connects to LED electrodes and conductors on the bottom substrate.

Abstract: A fabrication process employing the use of ScAlN as an etch mask is disclosed. The ScAlN etch mask is chemically nonvolatile in fluorine-based etch chemistries and has a low sputter yield, resulting in greater etch mask selectivity and reduced surface roughness for silicon and other semiconductor materials. The ScAlN etch mask has an etch mask selectivity of greater than 200,000:1 relative to silicon compared to an etch mask selectivity of less than 40,000:1 for a prior art AlN etch mask relative to silicon. Further, due to reduced sputtering of the ScAlN etch mask, and thus reduced micromasking, the ScAlN etch mask yielded a surface roughness of 0.6 ?m compared to a surface roughness of 2.8 ?m for an AlN etch mask.

Abstract: The various technologies presented herein relate to integrating an IC having at least one waveguide incorporated therein with a v-groove array IC such that an optical fiber located in a v-groove is aligned relative to a waveguide in the IC maximizing optical coupling between the fiber and the waveguide. The waveguide IC and the v-groove array IC are bonded in a stacked configuration. Alignment of the waveguide IC and the array IC in the stacked configuration enables advantage to be taken of lithographic accuracy of features formed with respect to the Z-direction. Further, kinematic pins and sockets are utilized to provision accuracy in the X- and Z-directions, wherein advantage is taken of the placement accuracy and fabrication tolerance(s) which can be utilized when forming the and sockets. Accordingly, automated alignment of the waveguide IC and the array IC is enabled, facilitating accurate alignment of the respective waveguides and fibers.

Abstract: A high current density, low contact resistance contact for wide bandgap (WBG) or ultra-wide bandgap materials (UWBG) is disclosed. The contact is lithographically formed so that a total perimeter length of the contact structure is at least twice the length of the side of a contact pad closest to the gate in a high electron mobility transistor (HEMT). The contact structure may take the form of a plurality of columns having various cross-sectional shapes, or may take the form of a convoluted geometrical shape, such as a comb-like, serpentine, or spiral shape. The depth of the contact structure permits direct contact with the two-dimensional electron gas (2DEG) in the HEMT by the perimeter of the contact structure. The contact structure is formed of at least one metal layer, at least one doped material regrown layer, or at least one implanted region. The contact structure may be applied to other WBG and UWBG devices.

Abstract: There is provided a near-zero-power wakeup system in which a MEMS sensor for mechanical or acoustic signals is coupled to a very-low-power complementary metal oxide semiconductor (CMOS) application-specific integrated circuit (ASIC). Power consumption can be minimized by operating the ASIC with sub-threshold gate voltages.

Abstract: The present invention relates to a lateral via to provide an electrical connection to a buried conductor. In one instance, the buried conductor is a through via that extends along a first dimension, and the lateral via extends along a second dimension that is generally orthogonal to the first dimension. In another instance, the second dimension is oblique to the first dimension. Components having such lateral vias, as well as methods for creating such lateral vias are described herein.

Abstract: A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. A transparent top substrate is then formed over the bottom substrate. Various ways to connect the LEDs in series are described along with many embodiments. In one method, the top substrate contains a conductor pattern that connects to LED electrodes and conductors on the bottom substrate.

Abstract: A micromechanical resonator is disclosed. The resonator includes a resonant micromechanical element. A film of annealable material deposited on a facial surface of the element. In one instance, the resonance of the element can be adjusting by using a feedback loop to control annealing of the deposited film.

Abstract: A radio frequency (RF) receiver comprises a passive impedance transforming voltage amplifier and a resonant, latching micromechanical switch having a deflectable bridge, an RF actuation electrode receivingly connected to the amplifier, and a DC bias electrode positioned to latch the switch in a closed position by electrostatic attraction when energized by a suitable voltage. The bridge is configured with a mechanical mode of vibration that periodically urges the switch toward the closed position.

Abstract: The present invention relates to a lateral via to provide an electrical connection to a buried conductor. In one instance, the buried conductor is a through via that extends along a first dimension, and the lateral via extends along a second dimension that is generally orthogonal to the first dimension. In another instance, the second dimension is oblique to the first dimension. Components having such lateral vias, as well as methods for creating such lateral vias are described herein.

Abstract: An optomechanical force sensor includes a substrate, a cantilevered beam anchored to the substrate, and a probe tip positioned near an end of the cantilevered beam distal to the substrate. A suspended waveguide is disposed on the cantilevered beam and is optically continuous with an input/output waveguiding structure. An optical cavity is defined within the suspended waveguide.

Abstract: The present invention relates to a lateral via to provide an electrical connection to a buried conductor. In one instance, the buried conductor is a through via that extends along a first dimension, and the lateral via extends along a second dimension that is generally orthogonal to the first dimension. In another instance, the second dimension is oblique to the first dimension. Components having such lateral vias, as well as methods for creating such lateral vias are described herein.

Abstract: The present invention relates to the use of gallium beam lithography to form superconductive structures. Generally, the method includes exposing a surface to gallium to form an implanted region and then removing material adjacent to and/or below that implanted region. In particular embodiments, the methods herein provide microstructures and nanostructures in any useful substrate, such as those including niobium, tantalum, tungsten, or titanium.

Abstract: The present invention relates to the design and manufacture of an ignitable solid, where the solid is composed of an array of ignitable regions. In some examples, the array provides a three-dimensional periodic arrangement of such ignitable regions. The ignitable region can have any useful geometry and geometric arrangement within the solid, and methods of making such regions are also described herein.