Patents by Inventor Michael David Hutton
Michael David Hutton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11714471Abstract: A system includes a programmable logic device (PLD) and a processor. The processor determines sets of power values associated with respective portions of a plurality of portions of the PLD. The processor also determines a temperature value for each portion of the plurality of portions based on the sets of power values and platform data associated with the PLD. Additionally, the processor generates a power map indicative of an expected amount of power for each portion of the plurality of portions based on the sets of power values. Furthermore, the processor generates a heat map indicative of an expected temperature value for each portion of the plurality of portions.Type: GrantFiled: September 23, 2021Date of Patent: August 1, 2023Assignee: Intel CorporationInventor: Michael David Hutton
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Publication number: 20230119235Abstract: A method and system for controlling performance of a workload partitioned among a plurality of accelerator chips of a multi-chip system. One or more processors may receive performance speed data for each of the accelerator chips, obtain a model of the partitioned workload, determine a portion of the workload that is either overworked or underworked based on the model of the partitioned workload and the performance speed data for each of the plurality of accelerator chips, and adjust a performance speed of an accelerator chip that performs the portion of the partitioned workload that is either overworked or underworked.Type: ApplicationFiled: October 18, 2022Publication date: April 20, 2023Inventors: Michael David Hutton, Georgios Konstadinidis, Lluis-Miquel Munguia, Safeen Huda, Gaurav Agrawal
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Publication number: 20220224656Abstract: Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.Type: ApplicationFiled: March 9, 2022Publication date: July 14, 2022Inventors: Michael David Hutton, Herman Henry Schmit, Dana How
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Publication number: 20220011838Abstract: A system includes a programmable logic device (PLD) and a processor. The processor determines sets of power values associated with respective portions of a plurality of portions of the PLD. The processor also determines a temperature value for each portion of the plurality of portions based on the sets of power values and platform data associated with the PLD. Additionally, the processor generates a power map indicative of an expected amount of power for each portion of the plurality of portions based on the sets of power values. Furthermore, the processor generates a heat map indicative of an expected temperature value for each portion of the plurality of portions.Type: ApplicationFiled: September 23, 2021Publication date: January 13, 2022Inventor: Michael David Hutton
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Patent number: 11194947Abstract: Systems and methods for detecting and managing errors in integrated circuits are provided. In one example, a system includes an integrated circuit that includes configuration memory that defines a circuit design implemented by the integrated circuit. The circuit design includes a plurality of regions. Additionally, the system is configured to determine a physical location of an error in the configuration memory and determine a location in a floorplan of the configuration memory that corresponds to the physical location of the error in the configuration memory. The floorplan identifies where the plurality of regions are defined in the configuration memory. The system is configured to determine in which of the plurality of regions the error in the configuration memory has occurred based at least in part on the location in the floorplan. Also, the system is configured to perform a corrective operation based on the location in the floorplan.Type: GrantFiled: September 27, 2017Date of Patent: December 7, 2021Assignee: Intel CorporationInventor: Michael David Hutton
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Patent number: 11137806Abstract: A system includes a programmable logic device (PLD) and a processor. The processor determines sets of power values associated with respective portions of a plurality of portions of the PLD. The processor also determines a temperature value for each portion of the plurality of portions based on the sets of power values and platform data associated with the PLD. Additionally, the processor generates a power map indicative of an expected amount of power for each portion of the plurality of portions based on the sets of power values. Furthermore, the processor generates a heat map indicative of an expected temperature value for each portion of the plurality of portions.Type: GrantFiled: January 12, 2018Date of Patent: October 5, 2021Assignee: Intel CorporationInventor: Michael David Hutton
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Patent number: 10678979Abstract: A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.Type: GrantFiled: July 14, 2017Date of Patent: June 9, 2020Assignee: Altera CorporationInventors: Michael David Hutton, Herman Henry Schmit
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Publication number: 20200136624Abstract: Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires, configuration bits for storing configurations for the functional blocks and routing wires, and local control circuitry for interfacing with the configuration bits to configure the sector. The programmable circuit may include global control circuitry for interfacing with the local control circuitry to configure the sector. Each sector may be independently operable and/or operable in parallel with other sectors. Operating the programmable circuit may include using the local control circuitry to interface with the configurations bit and configure the sector. Additionally, operating the programmable circuit may include using the global control circuitry to interface with respective local control circuitry and configure the sector.Type: ApplicationFiled: December 23, 2019Publication date: April 30, 2020Inventors: Dana How, Sean R. Atsatt, Michael David Hutton, Herman Henry Schmit
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Patent number: 10523207Abstract: Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires, configuration bits for storing configurations for the functional blocks and routing wires, and local control circuitry for interfacing with the configuration bits to configure the sector. The programmable circuit may include global control circuitry for interfacing with the local control circuitry to configure the sector. Each sector may be independently operable and/or operable in parallel with other sectors. Operating the programmable circuit may include using the local control circuitry to interface with the configurations bit and configure the sector. Additionally, operating the programmable circuit may include using the global control circuitry to interface with respective local control circuitry and configure the sector.Type: GrantFiled: August 15, 2014Date of Patent: December 31, 2019Assignee: Altera CorporationInventors: Dana How, Sean R. Atsatt, Michael David Hutton, Herman Henry Schmit
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Patent number: 10367756Abstract: Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.Type: GrantFiled: October 19, 2016Date of Patent: July 30, 2019Assignee: Altera CorporationInventors: Michael David Hutton, Herman Henry Schmit, Dana How
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Publication number: 20190215280Abstract: Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.Type: ApplicationFiled: March 19, 2019Publication date: July 11, 2019Inventors: Michael David Hutton, Herman Henry Schmit, Dana How
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Patent number: 10289483Abstract: A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without affecting the functionality of the circuit design. The CAD tool may compute an error check code (e.g., parity bits for a two-dimensional parity check) and insert the error check code into the configuration data. As an example, the CAD tool may replace don't care bits in the configuration data with the error code. The configuration data may be stored in configuration memory cells on a programmable integrated circuit, thereby implementing the circuit design with the error code on the programmable integrated circuit. During execution, the programmable integrated circuit may execute error checking and detect and correct errors in the configuration data based on the embedded error code.Type: GrantFiled: August 30, 2016Date of Patent: May 14, 2019Assignee: Altera CorporationInventors: Herman Henry Schmit, Michael David Hutton
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Patent number: 10248484Abstract: An integrated circuit may include a plurality of configuration random access memory (CRAM) sectors that configure logic sectors to perform user-defined functions. The logic circuits configured by the CRAM sectors may vary in their criticality to the operation of the integrated circuit. A prioritized error detection schedule may be provided to error detection circuitry, allowing a more frequent check of sectors that are used to configure logical circuitry that is critical to the operation of the integrated circuit. Upon detecting an error in a given CRAM sector, a sensitivity map may be used to determine the logical location corresponding to the errant CRAM sector. A sensitivity processor may assign a criticality level to the logical location, and appropriate corrective action for the errant CRAM sector may be determined based on the criticality level and the logical location corresponding to the sector.Type: GrantFiled: February 21, 2017Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Michael David Hutton, Sean R. Atsatt
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Publication number: 20190095570Abstract: Systems and methods for detecting and managing errors in integrated circuits are provided. In one example, a system includes an integrated circuit that includes configuration memory that defines a circuit design implemented by the integrated circuit. The circuit design includes a plurality of regions. Additionally, the system is configured to determine a physical location of an error in the configuration memory and determine a location in a floorplan of the configuration memory that corresponds to the physical location of the error in the configuration memory. The floorplan identifies where the plurality of regions are defined in the configuration memory. The system is configured to determine in which of the plurality of regions the error in the configuration memory has occurred based at least in part on the location in the floorplan. Also, the system is configured to perform a corrective operation based on the location in the floorplan.Type: ApplicationFiled: September 27, 2017Publication date: March 28, 2019Inventor: Michael David Hutton
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Publication number: 20190043737Abstract: A system includes a programmable logic device (PLD) and a processor. The processor determines sets of power values associated with respective portions of a plurality of portions of the PLD. The processor also determines a temperature value for each portion of the plurality of portions based on the sets of power values and platform data associated with the PLD. Additionally, the processor generates a power map indicative of an expected amount of power for each portion of the plurality of portions based on the sets of power values. Furthermore, the processor generates a heat map indicative of an expected temperature value for each portion of the plurality of portions.Type: ApplicationFiled: January 12, 2018Publication date: February 7, 2019Inventor: Michael David Hutton
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Publication number: 20180239665Abstract: An integrated circuit may include a plurality of configuration random access memory (CRAM) sectors that configure logic sectors to perform user-defined functions. The logic circuits configured by the CRAM sectors may vary in their criticality to the operation of the integrated circuit. A prioritized error detection schedule may be provided to error detection circuitry, allowing a more frequent check of sectors that are used to configure logical circuitry that is critical to the operation of the integrated circuit. Upon detecting an error in a given CRAM sector, a sensitivity map may be used to determine the logical location corresponding to the errant CRAM sector. A sensitivity processor may assign a criticality level to the logical location, and appropriate corrective action for the errant CRAM sector may be determined based on the criticality level and the logical location corresponding to the sector.Type: ApplicationFiled: February 21, 2017Publication date: August 23, 2018Applicant: Intel CorporationInventors: Michael David Hutton, Sean R. Atsatt
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Publication number: 20170316120Abstract: A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.Type: ApplicationFiled: July 14, 2017Publication date: November 2, 2017Inventors: Michael David Hutton, Herman Henry Schmit
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Patent number: 9740808Abstract: A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.Type: GrantFiled: October 26, 2016Date of Patent: August 22, 2017Assignee: Altera CorporationInventors: Michael David Hutton, Herman Henry Schmit
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Patent number: 9575862Abstract: A logic design may include control and datapath circuitry. The datapath circuitry may be implemented in a double modular redundancy arrangement that generates respective first and second data signals. The control circuitry may be implemented in a triple modular redundancy arrangement. Storage circuitry may be used to buffer the first and second data signals. Real-time error detection circuitry may perform real-time error detection operations on the first and second data signals. Background error checking circuitry may perform background error checking operations such as cyclic redundancy check calculations on configuration data. In response to an error detected by the real-time error detection circuitry, the circuitry may select between the buffered first and second data signals to produce the output data signal. The selection may be performed based on the background error checking operations and may be delayed relative to the real-time detection of the error.Type: GrantFiled: July 16, 2014Date of Patent: February 21, 2017Assignee: Altera CorporationInventors: Michael David Hutton, Dalon L. Westergreen
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Publication number: 20170046455Abstract: A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.Type: ApplicationFiled: October 26, 2016Publication date: February 16, 2017Inventors: Michael David Hutton, Herman Henry Schmit