Abstract: A semiconductor device comprising: a plurality of semiconductor chips; a first conductor and a second conductor arranged at opposite sides of the semiconductor chips, wherein the second conductor comprises a plurality of pillars, and wherein each of the semiconductor chips comprises: a first surface facing the first conductor; a first electrode arranged on the first surface and electrically coupled to the first conductor; a second surface opposite to the first surface; a second electrode arranged on the second surface and electrically coupled to a respective one of the pillars, and a control electrode arranged on the second surface and configured to switch a current flowing between the first electrode and the second electrode; a circuit board comprising openings penetrated by the plurality of pillars, wherein the circuit board further comprises an electrically insulating layer, a first conductive film and a second conductive film.

Abstract: There is provide a power semiconductor module comprising: a first substrate; a second substrate; a circuit board arranged between the first and second substrates; a first power semiconductor device T1, T2 comprising first and second power electrodes and arranged between the circuit board and the first substrate; and a second power semiconductor device T3, T4 comprising third and fourth power electrodes and arranged between the circuit board and the second substrate. The circuit board comprises a plurality of electrically conductive layers stacked with a plurality of electrically insulating layers along a stacking direction Z. At least one of the electrically insulating layers is arranged between adjacent ones of the electrically conductive layers. The plurality of electrically conductive layers comprises first, second and third electrically conductive layers which are spaced apart from one another along the stacking direction Z.

Abstract: There is provided a power semiconductor module, comprising: a switching circuit 1000 comprising high-side and low-side power semiconductor devices 1100, 1200, and a switching node AC between the high-side and low-side power semiconductor devices; and a substrate 50 comprising: an electrically insulating body 5; a first electrically conductive layer arranged on a first surface of the electrically insulating body that faces the switching circuit; and a second electrically conductive layer arranged on a second opposite surface of the electrically insulating body. The first electrically conductive layer comprises a first conductive track 4 electrically connected to the switching node AC, and the second electrically conductive layer comprises a second conductive track 16 for coupling to a heat removal structure 9. The first conductive track 4 does not overlap with the second conductive track 16 across the electrically insulating body 5.

Abstract: A power semiconductor includes a substrate comprising an electrically insulating body and a patterned electrically conductive layer arranged on a surface of the electrically insulating body, wherein the patterned electrically conductive layer comprises first, second and third conductive tracks which are spaced apart from one another; a first power semiconductor device T1 and/or T2 comprising first and second power electrodes; a second power semiconductor device T3 and/or T4 comprising third and fourth power electrodes; and a circuit board comprising a plurality of electrically conductive layers stacked with a plurality of electrically insulating layers along a stacking direction Z; and the plurality of electrically conductive layers comprises first, second and third electrically conductive layers which are spaced apart from one another along the stacking direction.

Abstract: There is provided a semiconductor device 1, comprising: a housing comprising a first housing electrode 4 and a second housing electrode 5 arranged at opposite sides of the housing; and a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5 and coupled to at least one of the first and second housing electrodes 4, 5 by pressure, wherein the plurality of semiconductor units 30 comprise a first semiconductor unit 30-1 and a second semiconductor unit 30-2 neighbouring the first semiconductor unit 30-1; wherein the first and/or second housing electrode comprises a plurality of pillars 10, and the plurality of pillars comprise a first pillar 10-1 and a second pillar 10-2 electrically coupled to the first and second semiconductor units 30-1, 30-2, respectively, and wherein a surface 16 of the first housing electrode 4 comprises a groove 15, and a width W1 of the groove 15 is less than a spacing S2 between the first pillar 10-1 and the second pillar 10-2.

Abstract: There is provided a semiconductor device 100, comprising: at least one semiconductor chip 5, and a structure 2 thermally coupled to the at least one semiconductor chip 5, wherein the structure 2 comprises a surface located within an interior of the semiconductor device, and the surface comprises a groove 12; and a sensor 16 comprising an optical fibre 13 passing through the groove 12, wherein the sensor 16 is configured to sense a temperature of the at least one semiconductor chip 5.

Abstract: A semiconductor device comprising: a plurality of semiconductor chips; a first conductor and a second conductor arranged at opposite sides of the semiconductor chips, wherein the second conductor comprises a plurality of pillars, and wherein each of the semiconductor chips comprises: a first surface facing the first conductor; a first electrode arranged on the first surface and electrically coupled to the first conductor; a second surface opposite to the first surface; a second electrode arranged on the second surface and electrically coupled to a respective one of the pillars, and a control electrode arranged on the second surface and configured to switch a current flowing between the first electrode and the second electrode; a circuit board comprising openings penetrated by the plurality of pillars, wherein the circuit board further comprises an electrically insulating layer, a first conductive film and a second conductive film.

Abstract: There is provided a semiconductor device 1 which comprises: a housing comprising a first housing electrode 5 and a second housing electrode 4 which are arranged at opposite sides of the housing; a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5; a plurality of pressure means 40 for applying pressure to the plurality of semiconductor units 30, respectively, wherein the plurality of pressure means 40 are arranged between the plurality of semiconductor units 30 and the first housing electrode 5; a first conductive structure 14 arranged between the plurality of pressure means 40 and the plurality of semiconductor units 30, wherein the plurality of semiconductor units 30 are electrically connected in parallel between the second housing electrode 4 and the first conductive structure 14; and a second conductive structure 18 configured to provide a current flow path from the first conductive structure 14 to the first housing electrode 5, the second

Abstract: There is provided a semiconductor device 1, comprising: a housing comprising a first housing electrode 4 and a second housing electrode 5 arranged at opposite sides of the housing; and a plurality of semiconductor units 30 arranged within the housing between the first and second housing electrodes 4, 5 and coupled to at least one of the first and second housing electrodes 4, 5 by pressure, wherein the plurality of semiconductor units 30 comprise a first semiconductor unit 30-1 and a second semiconductor unit 30-2 neighbouring the first semiconductor unit 30-1; wherein the first and/or second housing electrode comprises a plurality of pillars 10, and the plurality of pillars comprise a first pillar 10-1 and a second pillar 10-2 electrically coupled to the first and second semiconductor units 30-1, 30-2, respectively, and wherein a surface 16 of the first housing electrode 4 comprises a groove 15, and a width W1 of the groove 15 is less than a spacing S2 between the first pillar 10-1 and the second pillar 10-2.

Abstract: There is provided a semiconductor device 100, comprising: at least one semiconductor chip 5, and a structure 2 thermally coupled to the at least one semiconductor chip 5, wherein the structure 2 comprises a surface located within an interior of the semiconductor device, and the surface comprises a groove 12; and a sensor 16 comprising an optical fibre 13 passing through the groove 12, wherein the sensor 16 is configured to sense a temperature of the at least one semiconductor chip 5.