Abstract: The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation of a main processor. A program operating in main memory halts due to operational errors. The program code lines save to a cache. In the main processor, a pool of memory is reserved. A copy of the data from the nominally inaccessible supplementary processor registers also transfers to the reserved storage area for processing of the program needing debugging. After the program debugging is complete, a copy of the contents of the memory pool is restored to the memory of the target supplemental processor. A copy of the local store register state and remaining local store data returns to main memory.

Abstract: A method and a system for managing a computer system's multiple processors as devices. The operating system accesses the multiple processors using processor device modules loaded into the operating system to facilitate a communication between an application requesting access to a processor and the processor. A device-like access is determined for accessing each one of the processors similar to device-like access for other devices in the system such as disk drives, printers, etc. An application seeking access to a processor issues device-oriented instructions for processing data, and in addition, the application provides the processor with the data to be processed. The processor processes the data according to the instructions provided by the application.

Abstract: A system and method for loading software on a plurality of processors is presented. A processing unit (PU) retrieves a file from system memory and loads it into its internal memory. The PU extracts a processor type from the file's header which identifies whether the file should execute on the PU or a synergistic processing unit (SPU). If an SPU should execute the file, the PU DMA's the file to the SPU for execution. In one embodiment, the file is a combined file which includes both PU and SPU code. In this embodiment, the PU identifies one or more section headers included in the file which indicates embedded SPU code within the combined file. In this embodiment, the PU extracts the SPU code from the combined file and DMA's the extracted code to an SPU for execution.

Abstract: A system and method for an asymmetric heterogeneous multi-threaded operating system are presented. A processing unit (PU) provides a trusted mode environment in which an operating system executes. A heterogeneous processor environment includes a synergistic processing unit (SPU) that does not provide trusted mode capabilities. The PU operating system uses two separate and distinct schedulers which are a PU scheduler and an SPU scheduler to schedule tasks on a PU and an SPU, respectively. In one embodiment, the heterogeneous processor environment includes a plurality of SPUs. In this embodiment, the SPU scheduler may use a single SPU run queue to schedule tasks for the plurality of SPUs or, the SPU scheduler may use a plurality of run queues to schedule SPU tasks whereby each of the run queues correspond to a particular SPU.

Abstract: A system and method for grouping processors is presented. A processing unit (PU) initiates an application and identifies the application's requirements. The PU assigns one or more synergistic processing units (SPUs) and a memory space to the application in the form of a group. The application specifies whether the task requires shared memory or private memory. Shared memory is a memory space that is accessible by the SPUs and the PU. Private memory, however, is a memory space that is only accessible by the SPUs that are included in the group. When the application executes, the resources within the group are allocated to the application's execution thread. Each group has its own group properties, such as address space, policies (i.e. real-time, FIFO, run-to-completion, etc.) and priority (i.e. low or high). These group properties are used during thread execution to determine which groups take precedence over other tasks.

Abstract: Disclosed is a coherent cache system that operates in conjunction with non-homogeneous processing units. A set of processing units of a first configuration has conventional cache and directly accesses common or shared system physical and virtual address memory through the use of a conventional MMU (Memory Management Unit). Additional processors of a different configuration and/or other devices that need to access system memory are configured to store accessed data in compatible caches. Each of the caches is compatible with a given protocol coherent memory management bus interspersed between the caches and the system memory.

Abstract: A task queue manager manages the task queues corresponding to virtual devices. When a virtual device function is requested, the task queue manager determines whether an SPU is currently assigned to the virtual device task. If an SPU is already assigned, the request is queued in a task queue being read by the SPU. If an SPU has not been assigned, the task queue manager assigns one of the SPUs to the task queue. The queue manager assigns the task based upon which SPU is least busy as well as whether one of the SPUs recently performed the virtual device function. If an SPU recently performed the virtual device function, it is more likely that the code used to perform the function is still in the SPU's local memory and will not have to be retrieved from shared common memory using DMA operations.

Abstract: A system and method is provided to allow virtual devices that use a plurality of processors in a multiprocessor systems, such as the BE environment. Using this method, a synergistic processing unit (SPU) can either be dedicated to performing a particular function (i.e., audio, video, etc.) or a single SPU can be programmed to perform several functions on behalf of the other processors in the system. The application, preferably running in one of the primary (PU) processors, issues IOCTL commands through device drivers that correspond to SPUs. The kernel managing the primary processors responds by sending an appropriate message to the SPU that is performing the dedicated function. Using this method, an SPU can be virtualized for swapping multiple tasks or dedicated to performing a particular task.

Abstract: A system and a method for sharing a common system memory by a main processor and a plurality of secondary processors. The sharing of the common system memory enables the sharing of data between the processors. The data are loaded into the common memory by the main processor, which divides the data to be processed into data blocks. The size of the data blocks is equal to the size of the registers of the secondary processors. The main processor identifies an available secondary processor to process the first data block. The secondary processor processes the data block and returns the processed data block to the common system memory. The main processor may continue identifying available secondary processors and requesting the available secondary processors to process data blocks until all the data blocks have been processed.

Abstract: A system and method are provided to dedicate one or more processors in a multiprocessing system to performing encryption functions. When the system initializes, one of the synergistic processing unit (SPU) processors is configured to run in a secure mode wherein the local memory included with the dedicated SPU is not shared with the other processors. One or more encryption keys are stored in the local memory during initialization. During initialization, the SPUs receive nonvolatile data, such as the encryption keys, from nonvolatile register space. This information is made available to the SPU during initialization before the SPUs local storage might be mapped to a common memory map. In one embodiment, the mapping is performed by another processing unit (PU) that maps the shared SPUs' local storage to a common memory map.

Abstract: The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

Abstract: The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

Abstract: A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode.

Abstract: The present invention provides for authenticating code and/or data and providing a protected environment for execution. The present invention provides for dynamically partitioning and un-partitioning a local store for the authentication of code or data. The local store is partitioned into an isolated and non-isolated section. Code or data is loaded into the isolated section. The code or data is authenticated in the isolated section of the local store. After authentication, the code is executed. After execution, the memory within the isolated region of the attached processor unit is erased, and the attached processor unit de-partitions the isolated section within the local store.

Abstract: The intensity of specularly reflected light from an illuminated object is represented by an algebraic expression including multiplication, addition, and subtraction operations. The algebraic expression is used in an illumination model, where the illumination model describes the color and intensity of light reflected by the illuminated object. Light reflected by the illuminated object is composed of ambient, diffuse, and specular components. The specular terms used in the illumination model are equivalent in functional form to the diffuse terms, thereby accelerating the computation of color vector c defined by the illumination model. A modified algebraic expression representing specularly reflected light from an illuminated object is defined and used in the illumination model, thereby accelerating computation of color vector c.

Abstract: A process for preparing a fluorinated poly(arylene ether) comprising the repeating unit: 1

Abstract: The present invention provides an interactive medium for customizing virtual motorcycles, existing as rotational images rendered in 3D. This customizing allows customers to manually alter the appearance of a motorcycle, on a computer, by clicking on various motorcycle parts, paint colors, and accessories. Programming is provided to implement this system by CD-ROM or the web. Upon completing a customization, customers can purchase the product. Skilled information is available on-line to facilitate the customization. Also, a forum for auctioning used parts, selling motorcycles, and advertising motorcycle related services is available. Thus, the present invention offers a method and apparatus for visually customizing a motorcycle in an interactive medium, for buying and selling motorcycles and motorcycle accessories on-line, and for receiving mechanically skilled guidance on-line.

Abstract: A catalyst support comprises a porous gel of an inorganic substance, for example a refractory inorganic oxide, and has a surface area in the range 125 to 150 m.sup.2 /g, a mean pore diameter in the range 140 to 190 .ANG. with at least 80% of the pore volume contained in pores having a pore size range of 50 to 90 .ANG.. The invention also relates to catalysts based on such supports and to hydrocarbon conversion processes, for example reforming, carried out in the presence of hydrogen and employing said catalysts.

Abstract: A catalyst support comprises a porous gel of an inorganic substance, for example a refractory inorganic oxide, and has a surface area in the range 125 to 150 m.sup.2 /g, a mean pore diameter in the range 140 to 190 .ANG. with at least 80% of the pore volume contained in pores having a pore size range of 50 to 90 .ANG.. The invention also relates to catalysts based on such supports and to hydrocarbon conversion processes, for example reforming, carried out in the presence of hydrogen and employing said catalysts.

Abstract: An active lighting system including one or more light stands each supporting a plurality of individually adjustable colored light sources, and a keyboard unit having a plurality of switches and light intensity controlling elements which are touch operated so as to enable the intensity of the various lights in the system to be selectively varied to create a rhythm-to-color display.