Abstract: A system and method for generating multiple images on a video display device is described. The method comprises associating a panel of light pipes with a video display device. The video display device is configured to display an interlaced plurality of individual video signals. The plurality of video signals are displayed on the video display device such that each individual signal from the plurality of video signals is viewable from a plurality of different angles with respect to the video display device.

Abstract: A novel a circuit for driving a fan includes an output terminal for supplying the fan with drive power, a pulse width modulation driver, and a limiter. A first power terminal of the fan is held at a first voltage (e.g., 0V), and a second power terminal of the fan is coupled to the output terminal of the driver circuit. The PWM driver provides a series of fan drive pulses on the output terminal, and the limiter prevents the voltage on the output terminal from falling below a predetermined voltage. The predetermined voltage is greater than the first voltage at which the fan's first power terminal is held, and is sufficient to keep the fan in motion even when the duty cycle of the PWM signal is 0%. In a particular embodiment the limiter includes a voltage clamp. In a more particular embodiment, the voltage clamp is a diode. In another particular embodiment, the limiter includes a switch for combining a PWM signal with a DC voltage at an output.

Abstract: A novel a circuit for driving a fan includes an output terminal for supplying the fan with drive power, a pulse width modulation driver, and a limiter. A first power terminal of the fan is held at a first voltage (e.g., 0V), and a second power terminal of the fan is coupled to the output terminal of the driver circuit. The PWM driver provides a series of fan drive pulses on the output terminal, and the limiter prevents the voltage on the output terminal from falling below a predetermined voltage. The predetermined voltage is greater than the first voltage at which the fan's first power terminal is held, and is sufficient to keep the fan in motion even when the duty cycle of the PWM signal is 0%. In a particular embodiment the limiter includes a voltage clamp. In a more particular embodiment, the voltage clamp is a diode. In another particular embodiment, the limiter includes a switch for combining a PWM signal with a DC voltage at an output.

Abstract: Cache memory is managed to update the data stored in the cache regardless of whether the address being operated upon is designated as cache inhibited. In this way, the contents of the cache are coherent with main memory so that when the processor redesignates a noncacheable range of addresses to be cacheable, the cache does not need to be flushed. Read operations follow cache inhibit faithfully.

Abstract: An arrangement in which resistors are interposed on a bus line to attenuate reflected spurious pulses. The resistors are positioned on the bus so as not to be between a processor and its cache memory, but so as to be between the combination of the processor and cache memory and components such as a peripheral controller and a memory controller. The resistors reflect a portion of the pulse energy and attenuate the pulse energy passing through them. In another aspect of the invention, the traces making up the bus are arranged so that the intertrace distance is greater than a distance between the traces and an internal reference plane. This causes magnetic energy radiated by an aggressor trace to encounter the reference plane before it encounters a victim trace. This also reduces the amount of magnetic cross-coupling.

Abstract: The present invention provides an apparatus and method for use in a computer system, and particularly, a computer system employing memory devices having discrete capacity (i.e., 256K bit, 1M bit, etc.), such as random access memory (RAM). The present invention includes a central processing unit (CPU) coupled through a multiplexor to a plurality of contiguous banks of memory devices. In a typical embodiment, a user inserts a desired number of RAM memory devices having a particular memory capacity into the memory banks. A maximum memory address is defined for each bank as the address which would exist if the highest capacity memory devices available were utilized (e.g., 16M bit/device). On power-up, the CPU sequentially attempts to store the numerical address value of each possible memory address at that address location, from the highest possible contiguous address to the lowest, for the first memory bank.