Abstract: A system for storing data in a memory may include circuitry that may receive an address, a command and data. The circuitry may also determine a type of the command and generate a read control or write control signal dependent upon the type. The system may also include a plurality of sub-arrays and sense amplifiers. Each of the sub-arrays may include a plurality of memory cells. Each of the sense amplifiers may be coupled to a respective one of the plurality of sub-arrays and may read data stored in a first memory cell included in the respective sub-array. The system may also include one or more write driver circuits. A first write driver circuit may be coupled to at least two of the plurality of sub-arrays. The first write driver circuit may be configured to store data into a second memory cell in one of the at least two sub-arrays.

Abstract: A system and method for managing power in a memory, wherein the system may include a processor and a memory unit coupled to the processor. The memory unit may initialize an address decoder into a first power mode. In response to receiving a command and an address corresponding to a location within the memory unit, the memory unit may use the first stage of the address decoder to decode at least a portion of the address. The memory unit may further switch a selected portion of a second stage of the address decoder from the first power mode to the second power mode, wherein the selected portion of the second stage of the address decoder is selected dependent upon an output signal of the first stage of the address decoder.

Abstract: A system, a voltage regulator and a method for regulating power are disclosed, wherein the system may include a processor, a voltage regulator circuit, and a memory unit. The voltage regulator circuit may be configured to generate a first power supply voltage provided to the memory unit. The voltage regulator circuit may be further configured to adjust a voltage level of two output nodes dependent upon a level of the first power supply voltage and a level of a reference voltage. The voltage regulator circuit may be further configured to adjust the level of the first power supply signal dependent upon the level of at least one of the two output voltages. The voltage regulating circuit may also provide the first output voltage to the second output voltage via an impedance.

Abstract: A system and method for managing power in a memory, wherein the system may include a processor and a memory unit coupled to the processor. The memory unit may initialize an address decoder into a first power mode. In response to receiving a command and an address corresponding to a location within the memory unit, the memory unit may use the first stage of the address decoder to decode at least a portion of the address. The memory unit may further switch a selected portion of a second stage of the address decoder from the first power mode to the second power mode, wherein the selected portion of the second stage of the address decoder is selected dependent upon an output signal of the first stage of the address decoder.

Abstract: A system for storing data in a memory may include circuitry that may receive an address, a command and data. The circuitry may also determine a type of the command and generate a read control or write control signal dependent upon the type. The system may also include a plurality of sub-arrays and sense amplifiers. Each of the sub-arrays may include a plurality of memory cells. Each of the sense amplifiers may be coupled to a respective one of the plurality of sub-arrays and may read data stored in a first memory cell included in the respective sub-array. The system may also include one or more write driver circuits. A first write driver circuit may be coupled to at least two of the plurality of sub-arrays. The first write driver circuit may be configured to store data into a second memory cell in one of the at least two sub-arrays.

Abstract: A system, a voltage regulator and a method for regulating power are disclosed, wherein the system may include a processor, a voltage regulator circuit, and a memory unit. The voltage regulator circuit may be configured to generate a first power supply voltage provided to the memory unit. The voltage regulator circuit may be further configured to adjust a voltage level of two output nodes dependent upon a level of the first power supply voltage and a level of a reference voltage. The voltage regulator circuit may be further configured to adjust the level of the first power supply signal dependent upon the level of at least one of the two output voltages. The voltage regulating circuit may also provide the first output voltage to the second output voltage via an impedance.

Abstract: Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an SRAM array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank that causes the accessed sub-bank to go to an operating voltage, and isolating the accessed sub-bank from non accessed sub-banks, while maintaining a sleep voltage on a load memory array and each of the sub-banks through the regulator; comparing a voltage on the non accessed sub-banks to a voltage output of the regulator; and providing a sleep voltage level to all of the sub-banks through the regulator when the voltage on the non accessed sub-banks is less than the sleep voltage.

Abstract: Apparatus and methods are provided for concurrently selecting multiple arrays of memory cells when accessing a memory element. A memory element includes a first array of one or more memory cells coupled to a first bit line node, a second array of one or more memory cells coupled to a second bit line node, access circuitry for accessing a first memory cell in the first array, a first transistor coupled between the first bit line node and the access circuitry, and a second transistor coupled between the second bit line node and the access circuitry. A controller is coupled to the first transistor and the second transistor, and the controller is configured to concurrently activate the first transistor and the second transistor to access the first memory cell in the first array.

Abstract: Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an SRAM array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank that causes the accessed sub-bank to go to an operating voltage, and isolating the accessed sub-bank from non accessed sub-banks, while maintaining a sleep voltage on a load memory array and each of the sub-banks through the regulator; comparing a voltage on the non accessed sub-banks to a voltage output of the regulator; and providing a sleep voltage level to all of the sub-banks through the regulator when the voltage on the non accessed sub-banks is less than the sleep voltage.

Abstract: A memory device is provided that includes a memory cell, a voltage input, a plurality of bit lines, an amplifier connected to only a particular one of the bit lines, and a switch that is coupled to the amplifier and the voltage input. The switch is configured to prevent the voltage input from being electrically coupled to the amplifier when the plurality of bit lines are electrically floating.

Abstract: Apparatus are provided for memory elements and related computing modules. An exemplary memory element includes a first array of one or more memory cells, a second array of one or more memory cells, write selection circuitry associated with the first array, and read selection circuitry associated with the second array. The write selection circuitry and the read selection circuitry are configured to be activated concurrently.

Abstract: A memory device is provided that includes a memory cell, a voltage input, a plurality of bit lines, an amplifier connected to only a particular one of the bit lines, and a switch that is coupled to the amplifier and the voltage input. The switch is configured to prevent the voltage input from being electrically coupled to the amplifier when the plurality of bit lines are electrically floating.

Abstract: Apparatus and methods are provided for concurrently selecting multiple arrays of memory cells when accessing a memory element. A memory element includes a first array of one or more memory cells coupled to a first bit line node, a second array of one or more memory cells coupled to a second bit line node, access circuitry for accessing a first memory cell in the first array, a first transistor coupled between the first bit line node and the access circuitry, and a second transistor coupled between the second bit line node and the access circuitry. A controller is coupled to the first transistor and the second transistor, and the controller is configured to concurrently activate the first transistor and the second transistor to access the first memory cell in the first array.

Abstract: Apparatus are provided for memory elements and related computing modules. An exemplary memory element includes a first array of one or more memory cells, a second array of one or more memory cells, write selection circuitry associated with the first array, and read selection circuitry associated with the second array. The write selection circuitry and the read selection circuitry are configured to be activated concurrently.