Abstract: A method for facilitating a dual-bank filter coefficient RAM designed to switch banks automatically during the vertical blanking interval in a television application. The method and system of the present invention allows a micro controller to program a new set of filter coefficients in the memory bank not currently being used, automatically detect when all the coefficients have been written and then automatically switch banks during the vertical blanking interval in the television application.

Abstract: A method for managing vertical format converter line memories includes writing a number of first input video lines into the VFC line memories, writing an additional video line into the VFC line memories, and reading respective pixels of the first input video lines and the additional input video line from the VFC line memories in parallel. The reading of respective pixels is commenced prior to completion of the writing of the additional video line. A digital video receiving system includes a somewhat similarly configured video processor.

Abstract: An apparatus for delaying video line data between a sending device and a receiving device is provided. The apparatus includes a single port random access memory (“RAM”) and a processing arrangement including a first storage device coupled to the RAM and a second storage device coupled to the RAM.

Abstract: An apparatus and concomitant method for generating an OSD message by constructing an OSD bitstream defining a single field of OSD data. The OSD bitstream contains an OSD header and OSD data. An OSD unit retrieves pixel control information from the OSD header which is programmed by a processor of a decoding/displaying system. The OSD header contains information including various pointers, that are used to provide instructions as to the treatment of the OSD data. If a top field pointer and a bottom field pointer are set to an identical value in the OSD header, then the OSD unit will repeat each OSD line in the other field for an OSD region.

Abstract: An apparatus and concomitant method for generating an OSD message by constructing an OSD bitstream having OSD data defining a plurality of alternate OSD pixel lines. The OSD bitstream contains an OSD header and OSD data. An OSD unit retrieves pixel control information from the OSD header which is programmed by a processor of a decoding/displaying system. The OSD header contains information that is used to program a color palette of the OSD unit and to provide instructions as to the treatment of the OSD data. If the “Line Doubling Mode” is enabled in the OSD header, then the OSD unit will repeat each OSD line on the next line of video for an OSD region.

Abstract: An apparatus and concomitant method for generating an OSD message by constructing an OSD bitstream having a plurality of “one-bit” pixels. The OSD bitstream contains an OSD header and OSD data. An OSD unit retrieves pixel control information from the OSD header which is programmed by a processor of a decoding/displaying system. The OSD header contains information that is used to program a color palette of the OSD unit and to provide instructions as to the treatment of the OSD data. If the “Compressed Pixel Mode” is enabled in the OSD header, then the OSD unit will treat each bit of the OSD data as a “one-bit” pixel.

Abstract: An apparatus and concomitant method for generating an OSD message by constructing an OSD bitstream defining a plurality of "true color" pixels. The OSD bitstream contains an OSD header and OSD data. An OSD unit retrieves pixel control information from the OSD header which is programmed by a processor of a decoding/displaying system. The OSD header contains information that is used to program a color palette of the OSD unit and to provide instructions as to the treatment of the OSD data. If the "True Color Mode" is enabled in the OSD header, then the OSD unit will bypass the palette and treat the OSD data as true color pixels. Since the same chrominance components are shared between a pair of successive pixels, each successive set of four OSD data bytes represents the actual chrominance and luminance levels for two OSD pixels.

Abstract: In order to increase the speed of the transfer of control data to an OSD circuit, and to eliminate "holes" in memory caused by the use of memory mapped registers, dual use is made of the serial data port of the OSD circuit to accomplish two distinct tasks, serial transfer of graphics data and serial transfer of the control data. The on-screen display apparatus includes an OSD circuit for generating an graphics signal for display on a display screen, a controller coupled to the OSD circuit, for controlling the OSD circuit, and a VRAM including a first area for storing graphics data and a second area for storing control data for the OSD circuit. The VRAM has a parallel input/output port coupled to the controller and a serial output port coupled to the OSD circuit, the serial output port conveys the graphics data from the first area of the VRAM to the OSD circuit for processing and display.