Abstract: Using a process in accordance with the teachings of this invention, an integrated circuit may be fabricated providing refractory metal silicide layers, such as TiSi.sub.2, of differing thicknesses to provide optimal reductions in the sheet resistances of the regions in which refractory metal silicide layers are formed. In one embodiment of the present invention a field effect transistor having a polycrystalline silicon gate is fabricated to provide a gate having optimally minimized sheet resistance and source and drain regions having TiSi.sub.2 layers of the appropriate thickness to avoid punch-through leakage problems.