Patents by Inventor Michael E. Barsky
Michael E. Barsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6764573Abstract: Apparatuses (10, 100), and methods of using same, for the simultaneous thinning of the backside surfaces of a plurality of semiconductor wafers (W) using a non-crystallographic and uniform etching process, are described. The apparatuses (10, 100) include a fixture (12, 102) having a plurality of horizontal receptacles (14, 16, 18, 20, 104, 106, 108, 110) for receiving the semiconductor wafers (W). The loaded fixtures (12, 102) are then immersed into an etchant solution (36, 146) that is capable of isotropically removing a layer of semiconductor material from the backside surface of the semiconductor wafers (W). The etchant solution (36, 146) is preferably heated to about 40° C.-50° C. and constantly stirred with a magnetic stirring bar (48, 158). Once a sufficient period of time has elapsed, the thinned semiconductor wafers (W) are removed from the etchant solution (36, 146).Type: GrantFiled: October 11, 2001Date of Patent: July 20, 2004Assignee: Northrop Grumman CorporationInventors: Richard Lai, Harvey N. Rogers, Yaochung Chen, Michael E. Barsky
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Patent number: 6710379Abstract: A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.Type: GrantFiled: February 4, 2003Date of Patent: March 23, 2004Assignee: Northrop Grumman CorporationInventors: Michael Wojtowicz, Tsung-Pei Chin, Michael E. Barsky, Ronald W. Grundbacher
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Patent number: 6638366Abstract: Semiconductor wafer (11) are uniformly and thoroughly cleaned of particulate and organic contaminants by sweeping the wafer with a hydraulic broom that sprays cleaning solution onto the wafer. The broom contains an aspirating nozzle (3) for connection to a source of pressurized gas, such as nitrogen, and to a source of cleaning fluid, such as acetone, wherein cleaning fluid aspirated by the gas stream is expressed through the nozzle outlet to impact the surface of the wafer, dislodging particulate matter and dissolving organic contaminants. A programmed controller (9) controls movement of the hydraulic broom relative to the wafer to ensure that the entire surface is cleaned and permits a variety of sweeping patterns.Type: GrantFiled: May 15, 2001Date of Patent: October 28, 2003Assignee: Northrop Grumman CorporationInventors: Michael D. Lammert, Victor J. Watson, John M. DiMond, Michael E. Barsky
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Publication number: 20030141519Abstract: A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.Type: ApplicationFiled: February 4, 2003Publication date: July 31, 2003Applicant: TRW Inc.Inventors: Michael Wojtowicz, Tsung-Pei Chin, Michael E. Barsky, Ronald W. Grundbacher
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Patent number: 6551905Abstract: A method is provided for backside processing a semiconductor wafer (10) including applying a polymer based protective coating (16) on the wafer, depositing a barrier layer of ceramic (18) on the protective coating, and coating the ceramic layer with a thermoplastic based adhesive (20). Thereafter, the wafer (10) is bonded to a perforated substrate (22) and then lapped and polished to a desired thickness and patterned with an etch mask. A high temperature plasma etching process is then used to etch via holes in the wafer (10). After etching and subsequent backside processing, the adhesive layer (20) is dissolved in acetone to separate the wafer (10) from the substrate (22). The protective coating (16) is then dissolved with a solvent to separate the ceramic layer (18) from the finished wafer (10).Type: GrantFiled: October 20, 2000Date of Patent: April 22, 2003Assignee: TRW Inc.Inventors: Michael E. Barsky, Harvey N. Rogers, Vladimir Medvedev, Yaochung Chen, Richard Lai
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Publication number: 20030071009Abstract: Apparatuses (10, 100), and methods of using same, for the simultaneous thinning of the backside surfaces of a plurality of semiconductor wafers (W) using a non-crystallographic and uniform etching process, are described. The apparatuses (10, 100) include a fixture (12, 102) having a plurality of horizontal receptacles (14, 16, 18, 20, 104, 106, 108, 110) for receiving the semiconductor wafers (W). The loaded fixtures (12, 102) are then immersed into an etchant solution (36, 146) that is capable of isotropically removing a layer of semiconductor material from the backside surface of the semiconductor wafers (W). The etchant solution (36, 146) is preferably heated to about 40° C.-50° C. and constantly stirred with a magnetic stirring bar (48, 158). Once a sufficient period of time has elapsed, the thinned semiconductor wafers (W) are removed from the etchant solution (36, 146).Type: ApplicationFiled: October 11, 2001Publication date: April 17, 2003Inventors: Richard Lai, Harvey N. Rogers, Yaochung Chen, Michael E. Barsky
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Patent number: 6524899Abstract: A method of manufacturing a HEMT IC using a citric acid etchant. In order that gates of different sizes may be formed with a single etching step, a citric acid etchant is used which includes potassium citrate, citric acid and hydrogen peroxide. The wafer is first spin coated with a photoresist which is then patterned by optical lithography. The wafer is dipped in the etchant to etch the exposed semiconductor material. Metal electrodes are evaporated onto the wafer and the remaining photoresist is removed with solvent.Type: GrantFiled: September 21, 2000Date of Patent: February 25, 2003Assignee: TRW Inc.Inventors: Ronald W. Grundbacher, Richard Lai, Mark Kintis, Michael E. Barsky, Roger S. Tsai
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Patent number: 6515316Abstract: A HEMT device comprises a buffer layer disposed over a substrate. A partially-relaxed channel is disposed over the buffer layer and a barrier layer is disposed over the channel. A cap layer is disposed over the barrier layer and a gate is positioned on the barrier layer. A source and a drain are positioned on the barrier layer on opposite sides of the gate.Type: GrantFiled: July 14, 2000Date of Patent: February 4, 2003Assignee: TRW Inc.Inventors: Michael Wojtowicz, Tsung-Pei Chin, Michael E. Barsky, Ronald W. Grundbacher
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Publication number: 20020170579Abstract: Semiconductor wafer (11) are uniformly and thoroughly cleaned of particulate and organic contaminants by sweeping the wafer with a hydraulic broom that sprays cleaning solution onto the wafer. The broom contains an aspirating nozzle (3) for connection to a source of pressurized gas, such as nitrogen, and to a source of cleaning fluid, such as acetone, wherein cleaning fluid aspirated by the gas stream is expressed through the nozzle outlet to impact the surface of the wafer, dislodging particulate matter and dissolving organic contaminants. A programmed controller (9) controls movement of the hydraulic broom relative to the wafer to ensure that the entire surface is cleaned and permits a variety of sweeping patterns.Type: ApplicationFiled: May 15, 2001Publication date: November 21, 2002Inventors: Michael D. Lammert, Victor J. Watson, John M. DiMond, Michael E. Barsky
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Patent number: 6452221Abstract: An enhancement mode FET device (10) that employs a strained N-doped InAlAs charge shield layer (22) disposed on an intrinsic InAlAs barrier layer (20). A gate metal electrode (38) of the FET device (10) is controllably diffused through a recess (36) into the shield layer (22) to the barrier layer (20). The resulting enhancement mode device (10) provides an excellent Schottky barrier with a high barrier height that inhibits undesirable surface depletion effects through charge shielding by the shield layer (22) in the regions between the recess edge and the gate metal. Minimizing surface depletion effects makes the device more robust by making the surface less sensitive to processing conditions and long-term operation effects.Type: GrantFiled: September 21, 2000Date of Patent: September 17, 2002Assignee: TRW Inc.Inventors: Richard Lai, Ronald W. Grundbacher, Yaochung Chen, Michael E. Barsky
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Patent number: 6396679Abstract: A single-layer, metal-insulator-metal capacitor, a monolithic microwave integrated circuit including such capacitors, and a process of fabricating such capacitors. The capacitor has a single layer of insulating material between two metallic layers. At least one of the metallic layers has rounded corners, reducing the electric field at the corners, and so lessening the likelihood of breakdown. In one preferred embodiment, each metal layer has rounded corners. The capacitors can be fabricated by an optical lithographic process.Type: GrantFiled: October 18, 2000Date of Patent: May 28, 2002Assignee: TRW Inc.Inventors: Ronald W. Grundbacher, Richard Lai, Roger S. Tsai, Michael E. Barsky
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Patent number: 6383826Abstract: A method for determining the etch depth of a gate recess (26) in an InP based FET device (10). The source-drain, current-voltage (I-V) relationship is monitored during the etching process. As the etch depth increases, a kink is formed in the linear portion of the I-V relationship. When the kink current reaches a desired value, the etching is stopped. The kink current is a strong function of etch depth, so small differences in etch depth can be easily targeted. By controlling the etch depth, the characteristics of the transistor can be reproducibly controlled and optimized.Type: GrantFiled: October 18, 2000Date of Patent: May 7, 2002Assignee: TRW Inc.Inventors: Michael E. Barsky, Richard Lai, Ronald W. Grundbacher, Rosie M. Dia, Yaochung Chen
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Patent number: 6245687Abstract: A method for etching GaN material comprising configuring the GaN material as an anode in an electrochemical cell where the electrochemical cell is comprised of an anode, a cathode and an electrolyte, and applying a bias across the anode and the cathode to a level which is sufficient to induce etching of the material. The etch rate of the material is controllable by varying the bias level. The cell is additionally illuminated with a preselected level of UV light which provides for uniformity of the etching process. The present method is particularly useful for etching a GaN HBT from n-p-n GaN material.Type: GrantFiled: January 26, 2000Date of Patent: June 12, 2001Assignee: TRW Inc.Inventors: Michael E. Barsky, Rajinder R. Sandhu, Michael Wojtowicz