Abstract: The disclosure shows a read only storage (ROS) formed of a matrix of rows and columns of field effect transistor (FET) devices which is personalized by the presence or absence of a gate at the memory device location. All circuits on the chip are controlled and restored to initial conditions by a single train of clock pulses including the row and column addresses, the array select and the output sensing. In addition the output signal is communicated directly to the output line control device without withdrawing current to set the outputs latch thereby making the output truely delayless.