Abstract: A distributed wireless monitoring system with a cloud server and low-power remote sensors includes data encoding/compression at sensors to reduce power use from transmission and storage, event activated operation/data logging triggered by configurable thresholds, remote configuration via the cloud server of event triggering thresholds and correlation templates, distributed processing capabilities, and sensor clock synchronization from a network time service.

Abstract: A distributed wireless monitoring system with low-power remote sensors includes data encoding/compression at sensors to reduce power use from transmission and storage, event activated operation/data logging, remote configuration of event triggering thresholds and correlation templates, distributed processing capabilities, and sensor clock synchronization from a network time service.

Abstract: A distributed wireless monitoring system with low-power remote sensors includes data encoding/compression at sensors to reduce power use from transmission and storage (where the compact data representation is decoded after upload), event activated operation/data logging, remote configuration of event triggering thresholds and correlation templates, distributed processing capabilities, and sensor clock synchronization from a network time service.

Abstract: A digital signal processor on an integrated circuit uses a multi-port data flow structure characterized by four ports, referred to as an acquisition port, two data ports, and a coefficient port. All four ports may be bidirectional so that data may be read from and written to the respective ports by the DSP system. This architecture allows a data flow management scheme in which data enters the processor through the acquisition port, or any one of the data ports. As the data is processed, it may ping pong between the data ports, or between a data port and the acquisition port. At the end of a DSP algorithm, the output data may be provided through the acquisition port or a data port as suits the needs of the particular application. A coefficient port is typically used for providing coefficients or twiddle factors for DSP algorithms. A DSP system is provided which includes a digital signal processor having four ports as discussed above. Each data port is attached to dedicated, independent data memory.

Abstract: A one-chip address generator for producing a sequence of address signals for application to a memory containing a plurality of circular buffers. The address generator chip is capable of processing service requests from a plurality of channels on a prioritized basis. Service requests can arrive asynchronously at different rates. A channel-specific length or overlap value can be assigned to each servicing of a request. A seamless pipeline structure is provided for processing the service requests of subsequent channels immediately after completion of service for a first requesting channel.

Abstract: A digital array signal processor and an associated method are described for implementing the fast Fourier transform radix-4 butterfly algorithm. The digital array signal processor is an integrated circuit with a four stage pipeline and can perform a radix-4 butterfly operation on four complex operands every 80 nanoseconds. Using the decimation-in-frequency implementation of the radix-4 butterfly algorithm, the digital array signal processor includes a first stage for distribution of complex input operand values, a second stage for performing addition and subtraction operations, a third stage for performing multiplication operations and a fourth stage for distribution of the output operand values. The digital array signal processor can be reconfigured to perform a radix-2 butterfly operation on two sets of two complex numbers during the 80 nanosecond machine cycle as well as frequently used arithmetic and logic operations.

Abstract: A control apparatus for use with a digital signal processing device and associated memory units is described. The control apparatus determines, along with the electrical configuration of the digital signal processing device and associated memory units, the application of members of a signal array to be processed and the removal of the members of a processed signal array from the digital signal processing device. The control apparatus controls the location of data exchanged between the digital signal processing device and the associated memory units.