Patents by Inventor Michael E. Haslam

Michael E. Haslam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8339197
    Abstract: Matched bipolar transistor pairs for use in differential transistor pair circuitry, current mirror transistor pair circuitry and voltage reference transistor pair circuitry are disclosed. Each transistor in the pair includes a base, emitter and a collector region and a doped polysilicon emitter contact, a metal emitter contact and an metal emitter interconnect which makes an electrical connection to the emitter region by way of the metal emitter contact and the polysilicon emitter contact. The metal emitter interconnect is displaced latterly away from the emitter region so that no part of the metal emitter interconnect overlies any portion of the emitter region.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: December 25, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Kwok-Fu Chiu, Yih-Chyi Chong, Michael E. Haslam
  • Publication number: 20120139634
    Abstract: Matched bipolar transistor pairs for use in differential transistor pair circuitry, current mirror transistor pair circuitry and voltage reference transistor pair circuitry are disclosed. Each transistor in the pair includes a base, emitter and a collector region and a doped polysilicon emitter contact, a metal emitter contact and an metal emitter interconnect which makes an electrical connection to the emitter region by way of the metal emitter contact and the polysilicon emitter contact. The metal emitter interconnect is displaced latterly away from the emitter region so that no part of the metal emitter interconnect overlies any portion of the emitter region.
    Type: Application
    Filed: December 2, 2010
    Publication date: June 7, 2012
    Inventors: Kwok-Fu Chiu, Yih-Chyi Chong, Michael E. Haslam
  • Patent number: 5593920
    Abstract: A structure and method for forming contact structures in integrated circuits. A buffer layer is formed over an underlying conductive element. A first conductive layer is then deposited over the buffer layer and patterned to define a first interconnect layer. While the first interconnect layer is patterned, the buffer layer protects the underlying conductive element from damage. Portions of the buffer layer which are not covered by the first interconnect layer are then removed, and a second conductive layer is deposited over the integrated circuit. The second conductive layer is then anisotropically etched to form conductive sidewall spacers alongside the vertical sidewalls of the first interconnect layer, where at least one of the conductive sidewall spacers makes electrical contact with the underlying conductive element. Therefore, a conductive contact is made between the underlying conductive element and the first interconnect layer through at least one of the conductive sidewall spacers.
    Type: Grant
    Filed: April 12, 1994
    Date of Patent: January 14, 1997
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Michael E. Haslam, Charles R. Spinner, III
  • Patent number: 5331116
    Abstract: A structure and method for forming contact structures in integrated circuits. A buffer layer is formed over an underlying conductive element. A first conductive layer is then deposited over the buffer layer and patterned to define a first interconnect layer. While the first interconnect layer is patterned, the buffer layer protects the underlying conductive element from damage. Portions of the buffer layer which are not covered by the first interconnect layer are then removed, and a second conductive layer is deposited over the integrated circuit. The second conductive layer is then anisotropically etched to form conductive sidewall spacers alongside the vertical sidewalls of the first interconnect layer, where at least one of the conductive sidewall spacers makes electrical contact with the underlying conductive element. Therefore, a conductive contact is made between the underlying conductive element and the first interconnect layer through at least one of the conductive sidewall spacers.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: July 19, 1994
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Michael E. Haslam, Charles R. Spinner, III
  • Patent number: 5321211
    Abstract: A structure and method for forming contact vias in integrated circuits. An interconnect layer is formed on an underlying layer in an integrated circuit. A buffer region is then formed adjacent to the interconnect layer, followed by forming an insulating layer over the integrated circuit. Preferably, the insulating layer is made of a material which is selectively etchable over the material in the buffer region. A contact via is then formed through the insulating layer to expose a portion of the interconnect layer. During formation of the contact via, the buffer region acts as an etch stop and protects the underlying layer. The buffer region also ensures a reliable contact will be made in the event of an error in contact via placement.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: June 14, 1994
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Michael E. Haslam, Charles R. Spinner, III