Abstract: A method and apparatus for identifying and synchronizing to two different fields in a disk drive employs different synchronization or "sync" patterns to reduce the chances of mis-identifying and false-identifying a field. Two very distinct synchronization patterns have been found that satisfy the d=1, k=7 run-length constraints of a data code used in the disk drive. During operation, one sync pattern is searched for to identify and synchronize to its associated field, then the field itself is read. This procedure is then repeated for the other sync pattern and its associated field. Also, the phase of a preamble preceding each sync character is established, so that the number of comparisons needed to find either sync character is reduced. A sync detector operates on cell pairs, and has a selector that selects which sync pattern to search for. The sync detector also has special features that enable it to find preamble and DC Erase fields in the disk cell stream.

Abstract: The improved CMOS shift register consists of a series of alternating PMOS and NMOS pass gates driven by a single clock signal. Each gate consists of either one or more PMOS transistor(s), or one or more NMOS transistor(s). When the clock signal goes low, the PMOS gates turn on and pass bit values. At the same time the adjacent NMOS gates, which are driven by the same low clock signal, shut off and prevent the passed bit values from traveling any further. The bit values are thus held between adjacent PMOS and NMOS gates. When the clock signal next goes high, the NMOS gates turn on and pass the held bit values while the PMOS gates driven by the same high clock shut off. The gates are connected by circuitry which essentially holds the bit values passed through the first associated gate until they are passed through the second associated gate. The shift register may also include gated or non-gated refresh circuitry, which operates to maintain a passed bit value.