Patents by Inventor Michael E. Scaman

Michael E. Scaman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8201132
    Abstract: A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: June 12, 2012
    Assignee: International Business Machines Corporation
    Inventors: David L. DeMaris, Timothy G. Dunham, William C. Leipold, Daniel N. Maynard, Michael E. Scaman, Shi Zhong
  • Patent number: 8161421
    Abstract: A method of training an Optical Proximity Correction (OPC) model comprises symmetrizing a complex design to be a test pattern having orthogonal symmetry. Symmetrizing may comprise establishing a axis of symmetry passing through the design, thereby dividing the design into two portions; deleting one of the two portions; and mirror-imaging the other of the two portions about the axis of symmetry. The design may be centered.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: April 17, 2012
    Assignees: International Business Machines Corporation, Infineon Technologies AG
    Inventors: Ramya Viswanathan, Amr Y. Abdo, Henning Haffner, Oseo Park, Michael E. Scaman
  • Patent number: 7808257
    Abstract: A method and apparatus for the non-contact electrical test of both opens and shorts in electronic substrates. Top surface electrical test features are exposed to an ionization source under ambient conditions and the subsequent charge build up is measured as a drain current by probes contacting corresponding bottom surface features. Opens are detected by an absence of a drain current and shorts are detected by turning off the ionization source and re-measuring the bottom surface probes with a varying bias applied to each probe in the array.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: October 5, 2010
    Assignee: International Business Machines Corporation
    Inventors: Christopher W. Cline, Edward J. Yarmchuk, Vincent A. Arena, Donald A. Merte, Thomas Picunko, Brian J. Wojszynski, Charles J. Hendricks, Michael E. Scaman, Robert S. Olyha, Jr., Arnold Halperin
  • Publication number: 20100095254
    Abstract: A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
    Type: Application
    Filed: December 7, 2009
    Publication date: April 15, 2010
    Inventors: David L. DeMaris, Timothy G. Dunham, William C. Leipold, Daniel N. Maynard, Michael E. Scaman, Shi Zhong
  • Patent number: 7685544
    Abstract: A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: March 23, 2010
    Assignee: International Business Machines Corporation
    Inventors: David L. DeMaris, Timothy G. Dunham, William C. Leipold, Daniel N. Maynard, Michael E. Scaman, Shi Zhong
  • Patent number: 7673279
    Abstract: The present invention is an iterative method or procedure involving a series of optical proximity correction (OPC) process steps for refining an integrated circuit design layout on a wafer during a photolithographic process. The iterative method may be applied as a system and computer program to perform classifying and grouping edge fragments according to directional orientations, selecting an edge fragment or a combination of non-opposing edge fragments, calculating an edge placement error of the selected edge fragment and proximally shifting the edge fragment until a quality limitation is met.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: March 2, 2010
    Assignee: International Business Machines Corporation
    Inventor: Michael E. Scaman
  • Publication number: 20100042967
    Abstract: A method that purposely relaxes OPC algorithm constraints to allow post OPC mask shapes to elongate along one direction (particularly lowering the 1-dimensional MEEF in this direction with the result of an effectively overall lowered MEEF) to produce a pattern on wafer that is circular to within an acceptable tolerance.
    Type: Application
    Filed: August 14, 2008
    Publication date: February 18, 2010
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICA CORPORATION
    Inventors: Derren N. Dunn, Michael M. Crouse, Henning Haffner, Michael E. Scaman
  • Publication number: 20100005440
    Abstract: A method of training an Optical Proximity Correction (OPC) model comprises symmetrizing a complex design to be a test pattern having orthogonal symmetry. Symmetrizing may comprise establishing a axis of symmetry passing through the design, thereby dividing the design into two portions; deleting one of the two portions; and mirror-imaging the other of the two portions about the axis of symmetry. The design may be centered.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 7, 2010
    Applicants: International Business Machines Corporation, Infineon Technologies North America Corp
    Inventors: Ramya Viswanathan, Amr Y. Abdo, Henning Haffner, Oseo Park, Michael E. Scaman
  • Publication number: 20090191468
    Abstract: This disclosure includes a SRAF layout that minimizes the number of SRAFs required to reliably print contact shapes. A method is provided that reduces the number of necessary SRAF features on a mask, placing at least two elongated SRAF shapes on the mask such that the elongated SRAF shapes extend past at least one edge of a mask shape in at least one direction.
    Type: Application
    Filed: January 29, 2008
    Publication date: July 30, 2009
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICA CORPORATION
    Inventors: Michael M. Crouse, Derren N. Dunn, Henning Haffner, Michael E. Scaman
  • Publication number: 20080141203
    Abstract: The present invention is an iterative method or procedure involving a series of optical proximity correction (OPC) process steps for refining an integrated circuit design layout on a wafer during a photolithographic process. The iterative method may be applied as a system and computer program to perform classifying and grouping edge fragments according to directional orientations, selecting an edge fragment or a combination of non-opposing edge fragments, calculating an edge placement error of the selected edge fragment and proximally shifting the edge fragment until a quality limitation is met.
    Type: Application
    Filed: February 19, 2008
    Publication date: June 12, 2008
    Inventor: Michael E. Scaman
  • Patent number: 7360199
    Abstract: The present invention is an iterative method or procedure involving a series of optical proximity correction (OPC) process steps for refining an integrated circuit design layout on a wafer during a photolithographic process. The iterative method may be applied as a system and computer program to perform classifying and grouping edge fragments according to directional orientations, selecting an edge fragment or a combination of non-opposing edge fragments, calculating an edge placement error of the selected edge fragment and proximally shifting the edge fragment until a quality limitation is met.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: April 15, 2008
    Assignee: International Business Machines Corporation
    Inventor: Michael E. Scaman
  • Patent number: 7353472
    Abstract: A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: April 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: David L. DeMaris, Timothy G. Dunham, William C. Leipold, Daniel N. Maynard, Michael E. Scaman, Shi Zhong
  • Publication number: 20070277145
    Abstract: The present invention is an iterative method or procedure involving a series of optical proximity correction (OPC) process steps for refining an integrated circuit design layout on a wafer during a photolithographic process. The iterative method may be applied as a system and computer program to perform classifying and grouping edge fragments according to directional orientations, selecting an edge fragment or a combination of non-opposing edge fragments, calculating an edge placement error of the selected edge fragment and proximally shifting the edge fragment until a quality limitation is met.
    Type: Application
    Filed: May 26, 2006
    Publication date: November 29, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Michael E. Scaman
  • Patent number: 7187179
    Abstract: A wiring test structure includes a plurality of wiring traces configured in an interleaving spiral pattern. At least one of the plurality of wiring traces configured for open circuit testing therein, and at least a pair of the plurality of wiring traces is configured for short circuit testing therebetween.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: March 6, 2007
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Scaman, Toshiaki Yanagisawa
  • Patent number: 6400128
    Abstract: A system and method for locating a circuit defect, such as a short or an incipient open, in an electric circuit in a workpiece, such a Printed Circuit Board (PCB) or MultiChip Module (MCM). The circuit is connected to a device for sensitively measuring any resistance change. A thermal stimulus is applied to various subsets of the surface of the workpiece, the thermal stimulus being temporally modulated, and the resistance change measurement correlated with this modulation. By applying well-designed thermal stimulus subsets, resistance measurements may be logically combined which correspond to the plural thermal stimulus subsets. Further, the search region where the defect may be located may be iteratively refined. By measuring the time delay between the thermal stimulus and corresponding resistance change, the depth of a defect below the surface of the workpiece is further determined.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: June 4, 2002
    Assignee: International Business Machines Corporation
    Inventors: Daniel Guidotti, Arnold Halperin, Michael E. Scaman, Arthur R. Zingher
  • Publication number: 20010035748
    Abstract: A system and method for locating a circuit defect, such as a short or an incipient open, in an electric circuit in a workpiece, such a Printed Circuit Board (PCB) or MultiChip Module (MCM). The circuit is connected to a device for sensitively measuring any resistance change. A thermal stimulus is applied to various subsets of the surface of the workpiece, the thermal stimulus being temporally modulated, and the resistance change measurement correlated with this modulation. By applying well-designed thermal stimulus subsets, resistance measurements may be logically combined which correspond to the plural thermal stimulus subsets. Further, the search region where the defect may be located may be iteratively refined. By measuring the time delay between the thermal stimulus and corresponding resistance change, the depth of a defect below the surface of the workpiece is further determined.
    Type: Application
    Filed: March 19, 2001
    Publication date: November 1, 2001
    Inventors: Daniel Guidotti, Arnold Halperin, Michael E. Scaman, Arthur R. Zingher
  • Patent number: 6242923
    Abstract: A method of locating in a non-destructive and non-invasive manner power plane-to-power plane shorts or I/O net-to-power plane shorts found in a printed circuit board or a multi-chip-module by way of a magnetic field generating probe is described. Thousands of nets can be simultaneously tested to detect not only the presence of a short but also to accurately pinpoint its position. For high resistance shorts, the probe is provided with a pot core housed inductor located at its tip, and is used at low frequencies to minimize the effect of the capacitive impedance between the power planes. For low resistance shorts, the probe is used at high frequencies, delivering equal but opposite current to each of two matched inductors at the tip of the probe to maximize mutual inductive coupling while minimizing electrostatic capacitive coupling with the board or module. In both cases, the highest current stress is on the probe rather than on the expensive and fragile package under inspection.
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: June 5, 2001
    Assignee: International Business Machines Corporation
    Inventors: Michael E. Scaman, Edward J. Yarmchuk, Arnold Halperin
  • Patent number: 6236196
    Abstract: A system and method for locating a circuit defect, such as a short or an incipient open, in an electric circuit in a workpiece, such a Printed Circuit Board (PCB) or MultiChip Module (MCM). The circuit is connected to a device for sensitively measuring any resistance change. A thermal stimulus is applied to various subsets of the surface of the workpiece, the thermal stimulus being temporally modulated, and the resistance change measurement correlated with this modulation. By applying well-designed thermal stimulus subsets, resistance measurements may be logically combined which correspond to the plural thermal stimulus subsets. Further, the search region where the defect may be located may be iteratively refined. By measuring the time delay between the thermal stimulus and corresponding resistance change, the depth of a defect below the surface of the workpiece is further determined.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: May 22, 2001
    Assignee: International Business Machines Corporation
    Inventors: Daniel Guidotti, Arnold Halperin, Michael E. Scaman, Arthur R. Zingher
  • Patent number: 6141093
    Abstract: An apparatus and corresponding method for detecting, locating, or defining a short in a thin-film module. The apparatus includes a mechanical fixture supporting the module. A current source provides a current pulse to the module which produces a magnetic field and heating nearby the short which turns on and off as the pulsed current in the short turns on and off. Polarized light is directed onto the module, with an intermediate element disposed between the module and the source of the polarized light. The intermediate element may be a stress birefringent coating (e.g., a polyimide insulating layer) disposed on the module and onto which the polarized light is directed. The sample is rotated 0 to 45 degrees to maximize the birefringent effect. Alternatively, the intermediate element may be a magneto-optical Faraday rotator.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: October 31, 2000
    Assignee: International Business Machines Corporation
    Inventors: Bernell E. Argyle, Arnold Halperin, Michael E. Scaman, Edward J. Yarmchuk
  • Patent number: 5936408
    Abstract: A gas panel plasma plate is used to detect shorts and opens on a thin film surface of a multi-layer ceramic module (MCM) through biasing a circuit of the module through bottom surface module (BSM) pins to produce a glow within the plasma plate. A grounded plane is placed above the module to be tested, and the gap between the module and the plane is filled with a gas. A plasma discharge is created by biasing the circuit. The current produced at the BSM pin by the plasma discharge is monitored. The monitored current of the circuit under test is compared to a current range of a known good module. In the alternative, the light flux produced by the plasma discharge is monitored, and the monitored light flux is compared to a light flux range of a known good module.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: August 10, 1999
    Assignee: International Business Machines Corporation
    Inventor: Michael E. Scaman