Abstract: A monolithic integrated circuit for providing enhanced audio performance in personal computers. The monolithic circuit includes a wavetable synthesizer; a full function stereo coding and decoding circuit including analog-to-digital and digital-to-analog conversion; data compression, and mixing and muxing of analog signals; a local memory control module for interfacing with external memory; a game-MIDI port module; a system bus interface; and a control module for compatibility and circuit control functions.

Abstract: A configurable multiprocessor communications architecture which performs digital communications functions and which is configurable for different digital communications standards, such as various digital cellular standards. In the preferred embodiment, the multiprocessor architecture includes two or more digital signal processing cores, a microcontroller or micro-scheduler, a voice coder/decoder (codec), and a relatively low performance central processing unit (CPU). Each of the above devices are coupled to a system memory. The general purpose CPU preferably performs user interface functions and overall communications management functions. A CPU local memory and various peripheral devices are coupled through a CPU local bus to the CPU, and these devices are accessible to the CPU without the CPU having to access the main system bus. A dual port bus arbiter is preferably coupled between the CPU and the system bus and controls access to the system bus and the CPU local bus.

Abstract: A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data.

Abstract: A keypad scanner for a keypad having a plurality of keys which may be pressed into a down state includes circuitry for detecting when no or any key is pressed down and thereupon generating a no or any key down signal, circuitry for detecting when more than one key is pressed down and thereupon generating a multiple key down signal, and an interrupt generator coupled to the aforementioned circuitry. The interrupt generator itself includes circuitry for detecting a change in no or any key down signal level, circuitry for detecting a change in multiple key down signal level, and circuitry for generating an interrupt signal when either the circuitry for detecting a change in no or any key down signal level or the circuitry for detecting a change in multiple key down signal level detects a change.

Abstract: A memory cell is comprised of a cross-coupled master latch and a cross-coupled slave latch. The memory cell includes means for switching on and off power supplies connected to the master latch and the slave latch so as to control the direction of shift in a bidirectional shift. Data is shifted in a first direction when the power supply connected to the master latch is switched off, and data is shifted in a second direction when the power supply connected to the slave latch is switched off.

Abstract: A fracturable x-y random access memory array for performing pushing and popping of data and fracturing the array simultaneously at a common address includes a row fracture circuit responsive to row addresses to fracture the array in the Y-direction and a column fracture circuit responsive to column addresses for fracturing the array in the X-direction. A plurality of memory cells are stacked in a plurality of columns to form an x-y organization which can be randomly accessed in response to the row and column addresses. The memory cells are responsive to a shift control driver circuit for bidirectional shifting of data by either pushing data into or popping data from at any point within one of the plurality of randomly addressable column at the same row and column addresses used to fracture the array defining a fracture point.

Abstract: A method and data processing system for validating prefetch instruction. The system includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit. The system further includes a circuit for prefetching instruction words to be executed subsequently to a presently executing instruction and a circuit for verifying the validity of the prefetched instruction word prior to execution thereof by the execution unit, and a circuit for causing the instruction unit to a fault condition only when the execution of an invalid instruction is begun.

Abstract: A method and data processing system for validating prefetch instruction. The system includes an instruction unit, an n-stage pipeline which provides data segments representing instruction words from a memory to the instruction unit. The system further includes a circuit for prefetching instruction words to be executed subsequently to a presently executing instruction and a circuit for verifying the validity of the prefetched instruction word prior to execution thereof by the execution unit, and a circuit for causing the instruction unit to a fault condition only when the execution of an invalid instruction is begun.

Abstract: A microprocessor is disclosed having a bus controller which is capable of automatically performing multiple bus cycles in response to a multi-cycle signal received from the control unit. The bus controller includes means for automatically incrementing the access address provided by the control unit, and for controlling the transfer of the data between the bus and respective destinations in the control units.

Abstract: Each channel of a priority encoder register is equipped with a latch for storing one bit of a binary data word. The channel of highest priority generates an output which is applied to encoding means which in turn generates a unique code. The channel output is also fed back to reset its associated latch to permit the channel of next highest priority to generate an output.

Abstract: A data processor which is adapted for microprogrammed operation has a control store includes an ALU and condition code control unit for controlling operations performed by an arithmetic-logic unit within the execution unit of the data processor and for controlling the setting of the condition code bits in a status register. The ALU and condition code control unit is arranged in a row and column format. A decoder coupled to a macroinstruction register selects a row which is selected over an entire period that is required to execute macroinstruction. The row corresponds to a set of operations and condition code settings associated with a particular macroinstruction. The control store output provides information for selecting the proper column during each microcycle used to execute the macroinstruction. ALU function control signals and the condition code control signals are selected simultaneously according to the selected row and column.