Abstract: A computing system including a processor configured to receive a first stabilizer instrument specification of a first stabilizer instrument. The first stabilizer instrument specification includes a first input Clifford unitary, a first output Clifford unitary, and first stabilizer instrument bit matrices. The processor is further configured to receive a second stabilizer instrument specification of a second stabilizer instrument. The second stabilizer instrument specification includes a second input Clifford unitary, a second output Clifford unitary, and second stabilizer instrument bit matrices. Based at least in part on the first stabilizer instrument specification and the second stabilizer instrument specification, the processor is further configured to determine whether the first stabilizer instrument is equal to the second stabilizer instrument up to measurement outcome relabeling.

Abstract: A computing system is provided, including a processor configured to receive a standardized stabilizer instrument specification including an input Clifford unitary, an output Clifford unitary, and a plurality of stabilizer instrument bit matrices. The processor is further configured to receive a logical instrument input error correction code and a logical instrument output error correction code. The processor is further configured to compute a logical instrument specification based at least in part on the standardized stabilizer instrument specification, the logical instrument input error correction code, and the logical instrument output error correction code. The logical instrument specification includes a logical input Clifford unitary, a logical output Clifford unitary, a plurality of logical instrument bit matrices, and a logical instrument relabeling matrix. The processor is further configured to store the logical instrument specification in memory.

Abstract: A computing system including a processor configured to receive a stabilizer circuit specification of a stabilizer circuit that includes one or more elementary operations. The elementary operations are each selected from the group consisting of an allocation of one or more qubits in a stabilizer state, an allocation of one or more random classical bits, a Clifford unitary, a Pauli unitary conditional on respective parities of measurement outcomes and/or respective parities of the random classical bits, a joint multi-qubit Pauli measurement, and a destructive one-qubit Pauli measurement. The processor is further configured to compute a standardized stabilizer instrument specification of a stabilizer instrument based at least in part on the stabilizer circuit specification. The standardized stabilizer instrument specification includes an input Clifford unitary, an output Clifford unitary, and a plurality of bit matrices.

Abstract: A quantum computing device is provided, including a logical qubit encoding surface including a plurality of plaquettes. Each plaquette of the plurality of plaquettes may include a plurality of measurement-based qubits. The plurality of measurement-based qubits may include four data qubits and a first ancilla qubit. The first ancilla qubit may be electrically connected to the four data qubits and a second ancilla qubit included in the logical qubit encoding surface.

Abstract: A quantum decoder receives a syndrome from a quantum measurement circuit and performs various decoding operations for processing-efficient fault detection. The decoding operations include generating a decoding graph from the syndrome and growing a cluster around each one of multiple check nodes in the graph that correspond to a non-trivial value in the syndrome. Each cluster includes the check node corresponding to the non-trivial value and a set of neighboring nodes positioned within a distance of d edge-lengths from the check node. Following cluster growth, the decoder determines if, for each cluster, there exists a solution set internal to the cluster that fully explains the non-trivial syndrome bit for the cluster. If so, the decoder identifies and returns at least one solution set that fully explains the set of non-trivial bits in the syndrome.

Abstract: A disclosed methodology for syndrome extraction in a quantum measurement circuit includes generating a graph representing a code implemented by the quantum measurement circuit. The graph includes bit nodes corresponding to data qubits in the quantum measurement circuit, check nodes corresponding to syndrome qubits in the quantum measurement circuit, and edges between the bit nodes and check nodes that are each associated with a stabilizer measurement provided by the code. The methodology provides for assigning each of the different edges in the graph to a select one of “G” number of different edge types and performing at least G-number of temporally-separated rounds of qubit operations that each enact concurrent multi-qubit operations on endpoints of a subset of the edges assigned to a same one of the G different edge types.

Abstract: A quantum decoder receives a syndrome from a quantum measurement circuit and performs various decoding operations for processing-efficient fault detection. The decoding operations include generating a decoding graph from the syndrome and growing a cluster around each one of multiple check nodes in the graph that correspond to a non-trivial value in the syndrome. Each cluster includes the check node corresponding to the non-trivial value and a set of neighboring nodes positioned within a distance of d edge-lengths from the check node. Following cluster growth, the decoder determines if, for each cluster, there exists a solution set internal to the cluster that fully explains the non-trivial syndrome bit for the cluster. If so, the decoder identifies and returns at least one solution set that fully explains the set of non-trivial bits in the syndrome.

Abstract: A disclosed methodology for syndrome extraction in a quantum measurement circuit includes generating a graph representing a code implemented by the quantum measurement circuit. The graph includes bit nodes corresponding to data qubits in the quantum measurement circuit, check nodes corresponding to syndrome qubits in the quantum measurement circuit, and edges between the bit nodes and check nodes that are each associated with a stabilizer measurement provided by the code. The methodology provides for assigning each of the different edges in the graph to a select one of “G” number of different edge types and performing at least G-number of temporally-separated rounds of qubit operations that each enact concurrent multi-qubit operations on endpoints of a subset of the edges assigned to a same one of the G different edge types.

Abstract: A quantum measurement circuit implements a hypergraph product code (HPG). A syndrome can be extracted from the circuit by preparing a readout qubit of the quantum measurement circuit in a known state, preparing a row-based measurement gadget, and preparing a column-based measurement gadget in the quantum measurement circuit. The row-based measurement gadget entangles the readout qubit with a first subset of the target set of data qubits in a same row of the quantum measurement circuit as the readout qubit, and the column based gadget entangles the readout qubit with a second subset of the target set of data qubits in a same column of the quantum measurement circuit as the readout qubit. The syndrome is extracted by measuring the readout qubit to extract the parity of the target set of data qubits.

Abstract: A quantum computing device is provided, including a logical qubit encoding surface including a plurality of plaquettes. Each plaquette of the plurality of plaquettes may include a plurality of measurement-based qubits. The plurality of measurement-based qubits may include four data qubits and a first ancilla qubit. The first ancilla qubit may be electrically connected to the four data qubits and a second ancilla qubit included in the logical qubit encoding surface.