Abstract: Methods and System for use on a memory controller are disclosed which provides atomic compute operations of any size using an asynchronous, pipelined message passing interface between clients and the memory controller.

Abstract: The present subject disclosure presents a hardware mechanism and usage model for using a compute element of a systolic array to handle messages from an RQ (Receive Queue) to SQ (Send Queue) without requiring a copy between queues and also minimizing the local processor's interaction with the send and receive queue hardware.

Abstract: A system memory controller and method are disclosed providing a client preemption feature allowing performance optimizations for control firmware in a systolic array. The preemption feature allows clients with very different performance requirements and traffic patterns to share a central memory subsystem with minimal blocking and response latency issues.

Abstract: The present subject disclosure provides a PCIe switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.

Abstract: Systems and methods (including hardware and software) are disclosed where all common RAID storage levels are implemented for multi-queue hardware by isolating RAID stripes to a single central processing unit (CPU) core affinity. Fixed CPU affinity is used for any piece of data that may be modified. Instead of blocking CPUs that must access or modify a piece of data, the request is efficiently moved to the CPU that owns that data. In this manner the system is completely asynchronous, efficient, and scalable.

Abstract: Systems and methods (including hardware and software) are disclosed for us in a multi-core, multi-socket server with many RDMA network adapters and NVME solid state drives. One of the features of the subject matter is to optimize the total IO throughput of the system by first replacing software locks with non-interruptible event handlers running on specific CPU cores that own individual software data structures and hardware queues, and second by moving work to that CPU affinity without stalling due to software lock overhead.

Abstract: The present subject disclosure provides a PCIe switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.

Abstract: Systems and methods (including hardware and software) are disclosed where all common RAID storage levels are implemented for multi-queue hardware by isolating RAID stripes to a single central processing unit (CPU) core affinity. Fixed CPU affinity is used for any piece of data that may be modified. Instead of blocking CPUs that must access or modify a piece of data, the request is efficiently moved to the CPU that owns that data. In this manner the system is completely asynchronous, efficient, and scalable.

Abstract: A method of monitoring a sequence of documents passing along a transport path is described. The method including: operating a radiation transmitter with a control signal at a first, working, level to cause radiation at a first intensity to impinge on one side of a document as it passes an inspection position in the transport path; receiving at a radiation receiver, radiation from the transmitter that has passed through the document, the radiation receiver generating an output signal with a level related to the intensity of the received radiation; and monitoring the output signal to detect the presence and/or a characteristic of the document.

Abstract: A document handling apparatus is disclosed. The apparatus comprises an input module for feeding documents one-by-one into the machine, a note handling assembly including a note transport system, secure document analysis assembly, diverter and stacker module. The secure document analysis assembly includes one or more detectors for detecting characteristics of the documents. The diverter directs documents along one of plural transport paths. Documents pass from the diverter into a safe via a through-safe transport and transport safe module to a series of roll storage modules, in which documents can be stored and later dispensed.

Abstract: A method of monitoring a sequence of documents passing along a transport path is described. The method including: operating a radiation transmitter with a control signal at a first, working, level to cause radiation at a first intensity to impinge on one side of a document as it passes an inspection position in the transport path; receiving at a radiation receiver, radiation from the transmitter that has passed through the document, the radiation receiver generating an output signal with a level related to the intensity of the received radiation; and monitoring the output signal to detect the presence and/or a characteristic of the document.

Abstract: A document handling apparatus (100) is disclosed. The apparatus comprises an input module (500) for feeding documents one-by-one into the machine, a note handling assembly (400) including a note transport system, secure document analysis assembly, diverter and stacker module. The secure document analysis assembly includes one or more detectors for detecting characteristics of the documents. The diverter (800) directs documents along one of plural transport paths. Documents pass from the diverter into a safe via a through-safe transport and transport safe module to a series of roll storage modules, in which documents can be stored and later dispensed.