Patents by Inventor Michael Eric DAVIES

Michael Eric DAVIES has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Assigning workloads to physical resources in spatial architectures
    Patent number: 12717631
    Abstract: Operations of a workload are assigned to physical resources of a physical device array. The workload includes a graph of operations to be performed on a physical device array. The graph of operations is partitioned into subgraphs. Partitioning includes at least minimizing the quantity of subgraphs and maximizing resource utilization per subgraph. A logical mapping of the subgraph to logical processing engine (PE) units is generated using features of the subgraph and tiling factors of the logical PE units. The logical mapping is assigned to physical PE units of the physical device array at least by minimizing network traffic across the physical PE units. The operations of the subgraph are performed using the physical PE units to which the logical mapping is assigned. This process enhances the computational efficiency of the array when executing the workload.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: August 25, 2026
    Assignee: Microsoft Technology Licensing, LLC.
    Inventors: Fanny Nina Paravecino, Michael Eric Davies, Abhishek Dilip Kulkarni, Md Aamir Raihan, Ankit More, Aayush Ankit, Torsten Hoefler, Douglas Christopher Burger
  • ASSIGNING WORKLOADS TO PHYSICAL RESOURCES IN SPATIAL ARCHITECTURES
    Publication number: 20240303117
    Abstract: Operations of a workload are assigned to physical resources of a physical device array. The workload includes a graph of operations to be performed on a physical device array. The graph of operations is partitioned into subgraphs. Partitioning includes at least minimizing the quantity of subgraphs and maximizing resource utilization per subgraph. A logical mapping of the subgraph to logical processing engine (PE) units is generated using features of the subgraph and tiling factors of the logical PE units. The logical mapping is assigned to physical PE units of the physical device array at least by minimizing network traffic across the physical PE units. The operations of the subgraph are performed using the physical PE units to which the logical mapping is assigned. This process enhances the computational efficiency of the array when executing the workload.
    Type: Application
    Filed: February 24, 2023
    Publication date: September 12, 2024
    Inventors: Fanny NINA PARAVECINO, Michael Eric DAVIES, Abhishek Dilip KULKARNI, Md Aamir RAIHAN, Ankit MORE, Aayush ANKIT, Torsten HOEFLER, Douglas Christopher BURGER