Abstract: A method and apparatus for preserving the processing order of some requests in a system is disclosed. The method may include blocking requests from executing based on a blocked count data field, blocking list data field, and a last request data field. The apparatus may include a system or a memory device.

Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.

Abstract: A method includes receiving a request to access a disk drive. The request has a size. The method further includes selecting a queue, based at least in part on the size of the request, from among a plurality of queues, and assigning the request to the selected queue.

Abstract: Processor-based systems may include a disk cache to increase system performance in a system that includes a processor and a disk drive. The disk cache may include physical cache lines and virtual cache lines to improve cache insertion and eviction policies. The virtual cache lines may also be useful when recovering from failed requests.

Abstract: Method and apparatus to improve cache performance using interarrival times between demand requests are described.

Abstract: In one embodiment, the present invention includes a method for writing data to a disk if inserting the data into a cache, such as a disk cache associated with the disk, would cause a threshold of dirty data in the cache to be met or exceeded. Further, in certain embodiments, the cache may store data according to a first cache policy and a second cache policy. A determination of whether to store data according to the first or second policies may be dependent upon an amount of dirty data in the cache, in certain embodiments. In certain embodiments, the cache may include at least one portion reserved for clean data.

Abstract: Non-demand requests may be queued and delayed until pending demand requests to a cached disk subsystem have been completed. This may improve system responsiveness in some embodiments of the present invention. If, during an idle time, when a write back request is being handled, a new demand request is received, in some embodiments, the new demand request may be taken up, and the write back request stalled for later execution after the demand request. By providing a higher priority to a demand request to the cached disk subsystem, input/output requests may be satisfied more quickly, improving user responsiveness in some embodiments.

Abstract: Cache write back requests may be coalesced to reduce disk accesses and improve overall system performance in some embodiments of the present invention. Contiguous and non-contiguous data from more than one cache line may be coalesced into a single write back request and written back in one atomic write to the disk drive. This data may also be flushed from the disk cache in one request.

Abstract: Processor-based systems may include a disk cache to increase system performance in a system that includes a processor and a disk drive. The disk cache may include physical cache lines and virtual cache lines to improve cache insertion and eviction policies. The virtual cache lines may also be useful when recovering from failed requests.

Abstract: A method and apparatus for preserving the processing order of some requests in a system is disclosed. The method may include blocking requests from executing based on a blocked count data field, blocking list data field, and a last request data field. The apparatus may include a system or a memory device.

Abstract: A method and apparatus for a processor of a computer system to control a communication device through a bus interface having six interconnects. The bus interface's first interconnect is a transmission and reception interconnect that allows the computer system to transmit and receive signals from a communication device (such as a telephone line or a radio transceiver). The second interconnect is a primary processor communication interconnect which serves as the primary communication route between the processor and a radio transceiver's microcontroller, and which enables the processor to control the various components of the radio transceiver. The third interconnect is a secondary processor communication interconnect that relays urgent signals (such as status, interrupt, and reset signals) between the processor and the radio transceiver's microcontroller.