Abstract: To convert a value from an initial data format to a modified data format having a modified data format style, an accelerator unit executes a first instruction to convert the value from the initial data format to an intermediate data format in an intermediate data format style. The accelerator unit then rounds the value in the intermediate data format according to an intermediate rounding mode. After rounding the value, the accelerator unit executes a second instruction to convert the value to the modified data format in the modified data format style. Further, the accelerator unit rounds the value according to a modified rounding mode such that converting the value from the initial data format to the modified data format introduces a single rounding error.

Abstract: A scale register is configured to store a first set of block scale factors associated with a first input vector to an operation and a second set of block scale factors associated with a second input vector to the operation. A processing unit is configured to perform the operation based on the first input vector, a first scale factor selected from the first set based on user input, the second input vector, and a second scale factor selected from the second set based on the user input. In some cases, the operation is an outer product operation and the processing unit includes a matrix engine configured to perform the outer product. The elements of the first input vector and the second input vector can represent quantized values of elements represented in a first precision that is higher than a second precision of the quantized values.

Abstract: An accelerator unit (AU) includes tile registers configured to store matrices associated with a machine-learning model to be implemented. Further, the AU supports a tile read column instruction that reads a column of elements from a matrix stored in the tile registers. When executing a tile read column instruction for a matrix, the AU first determines whether a transposed clone of the matrix is stored in the tile registers. If there is no transposed clone stored the AU generates a transposed clone by performing row read and tile write commands using the matrix. After confirming a transposed clone of the matrix is in the tile registers, the AU reads the rows of the transposed clone corresponding to the column indicated in the tile read column instruction.

Abstract: A disclosed method for integer-to-floating-point data transfers includes intercepting, by a scheduler of a register file, a unit of register data from an external computing resource. The method also includes sorting, by the scheduler, the unit of register data into a first-in, first-out queue. Additionally, the method includes selecting, by the scheduler, a port of the register file based on a review of existing data pipelines to the register file. Furthermore, the method includes injecting, by the scheduler, the unit of register data into a data pipeline of the selected port, wherein the unit of register data is held in the first-in, first-out queue until previous register data is processed. Various other methods, devices, and systems are also disclosed.

Abstract: A method for executing an instruction by an arithmetic logic unit pipeline can include performing, by permutation circuitry, a permutation in response to an instruction that includes an arithmetic operation. The method can also include performing, by an arithmetic logic unit, the arithmetic operation in response to the instruction. Various other methods and systems are also disclosed.

Abstract: An integrated circuit that performs computations according to an out-of-order execution scheduling scheme can include a first computing region and a second computing region. Such an integrated circuit can also include (i) a first retirement register that stores results of computations performed by the first computing region, and (ii) a second retirement register, physically disposed in proximity to the second computing region, that stores results of computations performed by the second computing region. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A disclosed system includes a physical processor with a scheduler circuit. The scheduler circuit can be configured to: (1) pre-pick, from a set of delayed broadcast scheduler entries, a pre-picked set of scheduler entries that have each met a threshold cycle time, (2) pick for execution, from a set of ready scheduler entries, a picked ready scheduler entry that has met a source dependence cycle time, the set of ready scheduler entries including (A) a set of scheduler entries that have each met the source dependence cycle time, and (B) the pre-picked set of scheduler entries, and (3) delay a broadcast of a scheduler update to the set of delayed broadcast scheduler entries.

Abstract: A coprocessor such as a floating-point unit includes a pipeline that is partitioned into a first portion and a second portion. A controller is configured to provide control signals to the first portion and the second portion of the pipeline. A first physical distance traversed by control signals propagating from the controller to the first portion of the pipeline is shorter than a second physical distance traversed by control signals propagating from the controller to the second portion of the pipeline. A scheduler is configured to cause a physical register file to provide a first subset of bits of an instruction to the first portion at a first time. The physical register file provides a second subset of the bits of the instruction to the second portion at a second time subsequent to the first time.

Abstract: An approach is provided for implementing register based single instruction, multiple data (SIMD) lookup table operations. According to the approach, an instruction set architecture (ISA) can support one or more SIMD instructions that enable vectors or multiple values in source data registers to be processed in parallel using a lookup table or truth table stored in one or more function registers. The SIMD instructions can be flexibly configured to support functions with inputs and outputs of various sizes and data formats. Various approaches are also described for supporting very large lookup tables that span multiple registers.

Abstract: The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A data processing system includes a vector data processing unit that includes a shared scheduler queue configured to store in a same queue, at least one entry that includes at least a mask type instruction and another entry that includes at least a vector type instruction. Shared pipeline control logic controls a vector data path or a mask data path, based a type of instruction picked from the same queue. In some examples, at least one mask type instruction and the at least one vector type instruction each include a source operand having a corresponding shared source register bit field that indexes into both a mask register file and a vector register file. The shared pipeline control logic uses a mask register file or a vector register file depending on whether bits of the shared source register bit field identify a mask source register or a vector source register.

Abstract: Methods, systems, and apparatuses provide support for allowing thread forward progress in a processing system and that improves quality of service. One system includes a processor; a bus coupled to the processor; a memory coupled to the processor via the bus; and a floating point unit coupled to the processor via the bus, wherein floating point unit comprises hardware control logic operative to: store for each thread, by a scheduler of the floating point unit, a counter; increase, by the scheduler, a value of the counter for each thread corresponding to a thread when at least one source ready operation exist for the thread; compare, by the scheduler, the value of the counter to a predetermined threshold; and make other threads ineligible to be picked by the scheduler when the counter is greater than or equal to the predetermined threshold.

Abstract: A processor includes a plurality of execution pipes and a distributed scheduler coupled to the plurality of execution pipes. The distributed scheduler includes a first queue to buffer instruction operations from a front end of an instruction pipeline of the processor and a plurality of second queues, wherein each second queue is to buffer instruction operations allocated from the first queue for a corresponding separate subset of execution pipes of the plurality of execution pipes. The distributed scheduler further includes a queue controller to select an allocation mode from a plurality of allocation modes based on whether at least one indicator of an imbalance at the distributed scheduler is detected, and further to control the distributed scheduler to allocate instruction operations from the first queue among the plurality of second queues in accordance with the selected allocation mode.

Abstract: A processor includes one or more processor cores configured to perform accumulate top (ACCT) and accumulate bottom (ACCB) instructions. To perform such instructions, at least one processor core of the processor includes an ACCT data path that adds a first portion of a block of data to a first lane of a set of lanes of a top accumulator and adds a carry-out bit to a second lane of the set of lanes of the top accumulator. Further, the at least one processor core includes an ACCB data path that adds a second portion of the block of data to a first lane of a set of lanes of a bottom accumulator and adds a carry-out bit to a second lane of the set of lanes of the bottom accumulator.

Abstract: In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.

Abstract: A data processing system includes a vector data processing unit that includes a shared scheduler queue configured to store in a same queue, at least one entry that includes at least a mask type instruction and another entry that includes at least a vector type instruction. Shared pipeline control logic controls a vector data path or a mask data path, based a type of instruction picked from the same queue. In some examples, at least one mask type instruction and the at least one vector type instruction each include a source operand having a corresponding shared source register bit field that indexes into both a mask register file and a vector register file. The shared pipeline control logic uses a mask register file or a vector register file depending on whether bits of the shared source register bit field identify a mask source register or a vector source register.

Abstract: A processing unit includes a plurality of adders and a plurality of carry bit generation circuits. The plurality of adders add first and second X bit binary portion values of a first Y bit binary value and a second Y bit binary value. Y is a multiple of X. The plurality of adders further generate first carry bits. The plurality of carry bit generation circuits is coupled to the plurality of adders, respectively, and receive the first carry bits. The plurality of carry bit generation circuits generate second carry bits based on the first carry bits. The plurality of adders use the second carry bits to add the first and second X bit binary portions of the first and second Y bit binary values, respectively.

Abstract: An integrated circuit includes a vector data processing unit that employs a cross-lane shuffle unit including multiplexing logic that programmably shuffles packed source lane values, each corresponding to one of a plurality of vector lanes, to different output vector result lane positions over multiple cycles. In certain implementations, in a first cycle, control logic in the cross-shuffle unit controls the multiplexing logic to select source lane values to be placed in a first group of output vector result lane positions for a vector result register; and in at least a second cycle, the same multiplexing logic is reused to select source lane values to be placed in a second group of output vector result lane positions for the vector result register wherein at least one of the selected source lane values is moved to a different result lane position. Associated methods are also presented.

Abstract: The disclosed computer-implemented method for interpolating register-based lookup tables can include identifying, within a set of registers, a lookup table that has been encoded for storage within the set of registers. The method can also include receiving a request to look up a value in the lookup table and responding to the request by interpolating, from the encoded lookup table stored in the set of registers, a representation of the requested value. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.