Abstract: The present invention is a method to increase yield and performance (speed and power dissipation) of ICs. It involves identifying gates in a layout by location and classification (orientation and neighboring features), and applying mask correction to the gates based on these features, together with the location of the chip in the optical field. Mask correction is applied to each chip having a unique position within the optical field separately. Mask correction involves increasing or decreasing the line widths in the layout of the gate layer of those lines corresponding to transistor gates, depending on a spatial and category-based correction scheme. The present invention further includes a set of methods to determine the mask correction amounts, given limits in mask correction resolution, based on the spatial CD maps for each of the gate categories.