Abstract: Text data associated with multimedia content is transmitted to a mobile device while the multimedia content is shown on a separate network and remote apparatus. The mobile device requests the text data associated with the multimedia content and can optionally send hints to help determine which multimedia content text should be transmitted. The received text data is rendered in a scrollable, temporal representation, allowing recall of prior text associated with past multimedia content images.

Abstract: A method functions to resolve conflicts between wireless digital telephony and traditional analog telephony when an automatic telephone number dialer is concurrently used in a gateway. The method acts to prioritize telephone calls that operate using one telephone line when a single analog telephone line interfaces with an automatic telephone dialer and an analog telephone set in a system that also operates with a wireless digital telephone interface. The method includes detecting if an active call is present and determines if the telephone number being dialed is of higher priority than the active call. The highest priority call is placed or preserved according to the highest priority regardless of the source of the call in the system.

Abstract: A combined de-interlacing and frame doubling system (114, 114? and 114?) advantageously serves to de-interlace successive lines of Present Field Video data at twice the field rate to yield an output bit stream suitable for display on display device that utilizes progressive scanning. The de-interlacing and frame doubling system in accordance with present principles includes a frame memory mechanism (116, 116? and 116?) for storing at least one frame of interlaced video having a prescribed field rate. At least one de-interlacing circuit (11401, 1140?1, 1140?) pulls at least two fields of video data from the memory mechanism at a rate of at least twice the field rate for performing a full de-interlacing function in half of a field period to generate the a progressive, frame doubled signal for receipt at the display device.

Abstract: A method of converting interlaced video to progressive video can include a series of steps. The method can include receiving a video signal representative of at least one picture and determining whether the picture is progressive. If the picture is progressive, a vertical synchronization signal is modified to create an association with a first field of the picture. Accordingly, a progressive video signal can be converted to an interlaced video signal associated with the vertical synchronization signal and the interlaced video signal can then be converted to a progressive video signal in correspondence with modifications made to the vertical synchronization signal.

Abstract: A combined de-interlacing and frame doubling system (114, 114? and 114?) advantageously serves to de-interlace successive lines of Present Field Video data at twice the field rate to yield an output bit stream suitable for display on display device that utilizes progressive scanning. The de-interlacing and frame doubling system in accordance with present principles includes a frame memory mechanism (116, 116? and 116?) for storing at least one frame of interlaced video having a prescribed field rate. At least one de-interlacing circuit (11401, 1140?1, 1140?) pulls at least two fields of video data from the memory mechanism at a rate of at least twice the field rate for performing a full de-interlacing function in half of a field period to generate the a progressive, frame doubled signal for receipt at the display device.

Abstract: A method (300) of converting interlaced video (FIG. 2A) to progressive video can include a series of steps. The method can include receiving a video signal (310) representative of at least one picture and determining (320) whether the picture is progressive. If the picture is progressive, a vertical synchronization signal is modified to create an association with a first field of the picture (340). Accordingly, a progressive video signal can be converted to an interlaced video signal associated with the vertical synchronization signal and the interlaced video signal can then be converted to a progressive video signal in correspondence with modification made to the vertical synchronization signal (350).

Abstract: A combined de-interlacing and frame doubling system (114, 114′ and 114″) advantageously serves to de-interlace successive lines of Present Field Video data at twice the field rate to yield an output bit stream suitable for display on display device that utilizes progressive scanning. The de-interlacing and frame doubling system in accordance with present principles includes a frame memory mechanism (116, 116′ and 116″) for storing at least one frame of interlaced video having a prescribed field rate. At least one de-interlacing circuit (11401, 1140′1, 1140″) pulls at least two fields of video data from the memory mechanism at a rate of at least twice the field rate for performing a full de-interlacing function in half of a field period to generate the a progressive, frame doubled signal for receipt at the display device.

Abstract: A method (500) of converting interlaced video to progressive video can include receiving a video signal (505) representative of at least one picture and determining whether the at least one picture is progressive (510). Responsive to the progressive picture determination, a vertical synchronization signal can be selectively modified to identify whether a field previously sent and a field to immediately follow are from a same progressive picture (615, 640).

Abstract: A memory management process for buffering progressive, interlaced, CCIR 601/656 compliant, and MPEG compliant video signals in a video memory that is partitioned into first and second buffers. The process includes identifying the format of a received video signal, buffering the received video signal in the video memory in accordance with a standard buffering mode if the video signal is in an interlaced, CCIR 601/656 compliant, or MPEG compliant format, and buffering the received video signal in the video memory in accordance with an override buffering mode if the video signal is in a progressive format such as a 240p signal generated by a game console, VCR, cable text generator, and the like.

Abstract: A horizontal synchronizing system, comprising: a source of a horizontal synchronizing signal; a source of first and second higher frequency horizontal drive signals; a phase detector for generating a first control voltage responsive to the horizontal synchronizing signal and the first horizontal drive signal; a source of a second control signal; and, a switch for selectively supplying the first control signal to the source of the drive signals for a phase-locked mode of operation at the first higher frequency and supplying the second control signal to the source of the drive signals for a phase-unlocked mode of operation at the second higher frequency.

Abstract: A phase locked loop, comprising: a controllable oscillator requiring a control signal having a given bias voltage for generating a clock signal; an integrator for developing the control signal; a source of an external synchronizing signal; first and second voltage sources defining a voltage potential related to the given bias voltage; a first switch coupled to the first and second voltage sources and responsive to the clock signal for developing a regenerated clock signal having a peak to peak voltage determined by the voltage potential; and, a second switch responsive to the external synchronizing signal for periodically sampling portions of the regenerated clock signal and coupling the sampled portions to the integrator, the sampled portions charging and discharging the integrator to generate the control signal with a large enough magnitude to provide the given bias voltage, said first and second switches forming a phase detector.

Abstract: A phase locked loop, comprising: a controllable oscillator requiring a control signal having a given bias voltage for generating a clock signal; an integrator for developing the control signal; a source of an external synchronizing signal; first and second voltage sources defining a voltage potential related to the given bias voltage; a first switch coupled to the first and second voltage sources and responsive to the clock signal for developing a regenerated clock signal having a peak to peak voltage determined by the voltage potential; and, a second switch responsive to the external synchronizing signal for periodically sampling portions of the regenerated clock signal and coupling the sampled portions to the integrator, the sampled portions charging and discharging the integrator to generate the control signal with a large enough magnitude to provide the given bias voltage, said first and second switches forming a phase detector.