Abstract: An intermediate frequency signal (50) is received by a difference frequency generator (43). The intermediate frequency signal (50) includes a pilot tone frequency. A band pass filter (64) removes frequencies surrounding the pilot tone frequency. A phase lock loop (66) generates a pilot tone signal from the pilot tone frequency. A divisor (74) divides the frequency of the pilot tone signal by a specified number. A second phase detector (76) determines a frequency difference between the pilot tone signal and a stable frequency signal generated by a stable frequency oscillator (78). A control voltage for a difference frequency voltage controlled dielectric resonant oscillator (84) is adjusted based on the frequency difference. A system frequency signal (48) is downconverted to an intermediate frequency signal (50) using a difference frequency signal (54).

Abstract: Multipoint Stations are controlled by one or more pilot tones broadcasted by a base station. The pilot tones are used to control the local oscillators of the remote stations both for receive and for transmit. The pilot tone is also used to control the input gain and the transmit gain of the remote station.

Abstract: A phase locked loop ("PLL") 28 containing apparatus for automatically causing the PLL to achieve phase lock when first energized or after having lost phase lock. In addition to a phase detector 4, loop filter 13, voltage controlled oscillator ("VCO") 14 and feedback from the VCO to the phase detector 16, the PLL has a sweep circuit 30. The sweep circuit cooperates with the loop filter when the PLL is not in phase lock to automatically generate a control voltage for the VCO which control voltage increases linearly with time until the PLL achieves phase lock or until the control voltage has reached the largest voltage in the dynamic input range of the VCO. In the event that phase lock is not achieved during the period of the increasing voltage, the control voltage decreases linearly with time to drive the PLL into phase lock.

Abstract: A lock detection circuit for a phase lock loop circuit having a phase lock loop circuit, generally a series circuit of a detector, a filter and a VCO with a PLL input terminal and an output terminal. A test circuit is coupled to the phase lock loop and includes a signal generator responsive to the presence of an input signal on the input terminal to inject a test signal into the phase lock loop. The signal generator is preferably a low frequency oscillator wherein the term "low" is defined to mean any frequency from a few hertz up to gigahertz and generally a few kilohertz, as long as this frequency is at least about an order of magnitude less than the frequencies to be encountered at the RF input to the PLL. The signal generated by the signal generator is compared with the signal injected into the phase lock loop which is generally injected ahead of the loop filter.

Abstract: Apparatus and method for verifying the lock state or lock condition of a phase locked loop that includes a phase detector, a loop filter and a voltage controlled oscillator. The apparatus comprises a second oscillator that provides a signal of predetermined frequency to the loop filter and a second phase detector providing an output signal indicative of phase lock status. According to the method a signal of predetermined frequency is input to the loop filter and to a second phase detector. The presence of signals to the predetermined frequency is detected at the output of the loop phase detector by inputing the output from the loop phase detector to the second phase detector.