Patents by Inventor Michael F. Deering

Michael F. Deering has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200020308
    Abstract: A display device is mounted on and/or inside the eye. The eye mounted display contains multiple sub-displays, each of which projects light to different retinal positions within a portion of the retina corresponding to the sub-display. The projected light propagates through the pupil but does not fill the entire pupil. In this way, multiple sub-displays can project their light onto the relevant portion of the retina. Moving from the pupil to the cornea, the projection of the pupil onto the cornea will be referred to as the corneal aperture. The projected light propagates through less than the full corneal aperture. The sub-displays use spatial multiplexing at the corneal surface. Various electronic devices interface to the eye mounted display.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 16, 2020
    Inventors: Michael F. Deering, Alan Huang
  • Patent number: 10467992
    Abstract: A display device is mounted on and/or inside the eye. The eye mounted display contains multiple sub-displays, each of which projects light to different retinal positions within a portion of the retina corresponding to the sub-display. The projected light propagates through the pupil but does not fill the entire pupil. In this way, multiple sub-displays can project their light onto the relevant portion of the retina. Moving from the pupil to the cornea, the projection of the pupil onto the cornea will be referred to as the corneal aperture. The projected light propagates through less than the full corneal aperture. The sub-displays use spatial multiplexing at the corneal surface. Various electronic devices interface to the eye mounted display.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: November 5, 2019
    Assignee: Tectus Corporation
    Inventors: Michael F. Deering, Alan Huang
  • Publication number: 20190012989
    Abstract: A display device is mounted on and/or inside the eye. The eye mounted display contains multiple sub-displays, each of which projects light to different retinal positions within a portion of the retina corresponding to the sub-display. The projected light propagates through the pupil but does not fill the entire pupil. In this way, multiple sub-displays can project their light onto the relevant portion of the retina. Moving from the pupil to the cornea, the projection of the pupil onto the cornea will be referred to as the corneal aperture. The projected light propagates through less than the full corneal aperture. The sub-displays use spatial multiplexing at the corneal surface. Various electronic devices interface to the eye mounted display.
    Type: Application
    Filed: August 28, 2018
    Publication date: January 10, 2019
    Inventors: Michael F. Deering, Alan Huang
  • Patent number: 10019777
    Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: July 10, 2018
    Assignee: GULA CONSULTING LIMITED LIABILITY COMPANY
    Inventors: Michael F. Deering, Michael G. Lavelle
  • Publication number: 20170103494
    Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
    Type: Application
    Filed: October 21, 2016
    Publication date: April 13, 2017
    Inventors: Michael F. Deering, Michael G. Lavelle
  • Patent number: 9478001
    Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: October 25, 2016
    Assignee: GULA CONSULTING LIMITED LIABILITY COMPANY
    Inventors: Michael F. Deering, Michael G. Lavelle
  • Publication number: 20140204003
    Abstract: A display device is mounted on and/or inside the eye. The eye mounted display contains multiple sub-displays, each of which projects light to different retinal positions within a portion of the retina corresponding to the sub-display. The projected light propagates through the pupil but does not fill the entire pupil. In this way, multiple sub-displays can project their light onto the relevant portion of the retina. Moving from the pupil to the cornea, the projection of the pupil onto the cornea will be referred to as the corneal aperture. The projected light propagates through less than the full corneal aperture. The sub-displays use spatial multiplexing at the corneal surface. Various electronic devices interface to the eye mounted display.
    Type: Application
    Filed: March 26, 2014
    Publication date: July 24, 2014
    Inventors: Michael F. Deering, Alan Huang
  • Patent number: 8786675
    Abstract: A display device is mounted on and/or inside the eye. The eye mounted display contains multiple sub-displays, each of which projects light to different retinal positions within a portion of the retina corresponding to the sub-display. The projected light propagates through the pupil but does not fill the entire pupil. In this way, multiple sub-displays can project their light onto the relevant portion of the retina. Moving from the pupil to the cornea, the projection of the pupil onto the cornea will be referred to as the corneal aperture. The projected light propagates through less than the full corneal aperture. The sub-displays use spatial multiplexing at the corneal surface. Various electronic devices interface to the eye mounted display.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: July 22, 2014
    Inventor: Michael F. Deering
  • Publication number: 20140055485
    Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
    Type: Application
    Filed: November 5, 2013
    Publication date: February 27, 2014
    Applicant: ALANDRO CONSULTING NY LLC
    Inventors: Michael F. Deering, Michael G. Lavelle
  • Patent number: 8593468
    Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: November 26, 2013
    Assignee: Alandro Consulting NY LLC
    Inventors: Michael F. Deering, Michael G. Lavelle
  • Publication number: 20110221742
    Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
    Type: Application
    Filed: October 5, 2010
    Publication date: September 15, 2011
    Inventors: Michael F. Deering, Michael G. Lavelle
  • Patent number: 7808505
    Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: October 5, 2010
    Inventors: Michael F. Deering, Michael G. Lavelle
  • Patent number: 7587582
    Abstract: A method and apparatus for efficiently performing graphic operations are provided. This is accomplished by providing a processor that supports any combination of the following instructions: parallel multiply-add, conditional pick, parallel averaging, parallel power, parallel reciprocal square root and parallel shifts.
    Type: Grant
    Filed: August 16, 2000
    Date of Patent: September 8, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Subramania Sudharsanan, Jeffrey Meng Wah Chan, Michael F. Deering, Marc Tremblay, Scott R. Nelson
  • Publication number: 20090189974
    Abstract: A display device is mounted on and/or inside the eye. The eye mounted display contains multiple sub-displays, each of which projects light to different retinal positions within a portion of the retina corresponding to the sub-display. The projected light propagates through the pupil but does not fill the entire pupil. In this way, multiple sub-displays can project their light onto the relevant portion of the retina. Moving from the pupil to the cornea, the projection of the pupil onto the cornea will be referred to as the corneal aperture. The projected light propagates through less than the full corneal aperture. The sub-displays use spatial multiplexing at the corneal surface. Various electronic devices interface to the eye mounted display.
    Type: Application
    Filed: January 26, 2009
    Publication date: July 30, 2009
    Inventor: Michael F. Deering
  • Publication number: 20090189830
    Abstract: A display device is mounted on and/or inside the eye. The eye mounted display contains multiple sub-displays, each of which projects light to different retinal positions within a portion of the retina corresponding to the sub-display. The projected light propagates through the pupil but does not fill the entire pupil. In this way, multiple sub-displays can project their light onto the relevant portion of the retina. Moving from the pupil to the cornea, the projection of the pupil onto the cornea will be referred to as the corneal aperture. The projected light propagates through less than the full corneal aperture. The sub-displays use spatial multiplexing at the corneal surface.
    Type: Application
    Filed: January 23, 2009
    Publication date: July 30, 2009
    Inventors: Michael F. Deering, Alan Huang
  • Patent number: 7474308
    Abstract: A method and computer graphics system capable of super-sampling and performing real-time convolution are disclosed. In one embodiment, the computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples. The sample buffer, which is coupled to the graphics processor, may be configured to store the samples. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the sample buffer to filter into an output pixel. The sample-to-pixel calculation unit performs the filter process in real-time, and may use a number of different filter types in a single frame. The sample buffer may be super-sampled, and the samples may be positioned according to a regular grid, a perturbed regular grid, or a stochastic grid.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: January 6, 2009
    Assignee: Sun Microsystems, Inc.
    Inventor: Michael F. Deering
  • Publication number: 20080266300
    Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
    Type: Application
    Filed: May 27, 2008
    Publication date: October 30, 2008
    Inventors: Michael F. Deering, Michael G. Lavelle
  • Patent number: 7379067
    Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: May 27, 2008
    Inventors: Michael F. Deering, Michael G. Lavelle
  • Patent number: 7199806
    Abstract: A graphical computing system comprising a control unit and a set of edge processing units. The control unit (a) receives a surface primitive, (b) transfers edge specifying information for each edge of the surface primitive to a corresponding one of the edge processing units, and (c) transfers a horizontal address CX and a vertical address CY of a current pixel to the edge processing units. Each of the edge processing units computes trimming information for the current pixel with respect to the corresponding edge using the horizontal address CX and vertical address CY. The trimming information specifies a portion of the corresponding edge which intersects the current pixel. The control unit collects the trimming information from the edge processing units and transmits an output packet including the addresses CX and CY of the current pixel along with the collected trimming information.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: April 3, 2007
    Assignee: Sun Microsystems, Inc.
    Inventor: Michael F. Deering
  • Patent number: 7148890
    Abstract: A processing pipeline and method are disclosed that may enable real time video rate displacement mapping. The pipeline may include one or more: render units, texture units, memories, and displacement units. Render units may tessellate a geometric primitive into micropolygons and interpolate parameter values for each new vertex. The micropolygons may be defined by the intersection of the geometric primitive and boundaries projected from specified screen space regions. Texture units retrieve displacement values from a displacement map stored in memory. Displacement units displace each vertex of a micropolygon in the direction of the normal at each vertex by a distance based on the displacement value determined for the vertex location. Micropolygons that are displaced across a projected boundary may be returned to the render units and re-tessellated according to the projected boundaries. Parameter values for new vertices may be determined subject to an edge contract to prevent surface cracks.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: December 12, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Daniel S. Rice, Michael F. Deering