Abstract: A method and apparatus is provided for testing self timed memory arrays which does not affect the state of cells within the arrays not being tested. Each memory array has a plurality of control, address and data registers which are coupled to the respective control, address and data lines into the memory array. A timing generator circuit receives an external clock pulse and provides the self-timed clock pulses to the memory array. During the shift mode, the control, address and data registers are chained together such that data for testing can be scanned serially into the registers. In order to prevent unplanned array modification operations from occurring during the shift mode because a bit shifted into the write-enable or clear register at the time a clock pulse derived from the timing circuitry is generated, a logic means is provided to disable all clock pulses during the shift mode.