Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first select signal, a second select signal and a first data stream in response to an input data stream and an exception signal. The second circuit may be configured to generate an output data stream in response to the first data stream, the first select signal and the second select signal. The second circuit may be configured to replace one or more characters of the first data stream.

Abstract: An apparatus comprising a register circuit, a detector circuit and an output circuit. The register circuit may be configured to present a parallel signal in response to (i) a serial input and (ii) a first clock. The detector circuit may be configured to generate a control signal in response to (i) the parallel signal and (ii) a selection signal. The output circuit may be configured to generate an output in response to (i) the control signal and (ii) the parallel signal.

Abstract: An apparatus comprising a memory section and a first circuit. The memory section may be configured to present a first output in response to (i) a first clock signal, (ii) a second clock signal, (iii) an input pulse and (iv) the first output. The first circuit may be configured to generate a second output in response to (i) the first output and (ii) the second clock signal, where the second output may comprise a pulse having a width equal to a period of the second clock signal. In one example, an input circuit may be configured to present the first output to the memory section in response to the input pulse and a first feedback of the output.

Abstract: A buffer comprising a plurality of storage elements, a write pointer configured to indicate a particular storage element to write data received from an input data stream and a plurality of read pointers, each configured to indicate a particular data location to read data from to generate a number of output data streams. The input data stream and the output data streams may be part of a data communications device.

Abstract: A buffer comprising a plurality of storage elements, a write pointer configured to indicate a particular storage element to write data received from an input data stream and a plurality of read pointers, each configured to indicate a particular data location to read data from to generate a number of output data streams. The input data stream and the output data streams may be part of a data communications device.

Abstract: A circuit for measuring the frequency difference between a reference clock and a second clock. The circuit presents a first output in response to a phase crossing between the two clocks. A second circuit presents a second output in response to the first output and the reference clock.

Abstract: A reconfigurable buffer circuit capable of producing an active high or an active low output signal in accordance with a stored control parameter that is input to the buffer circuit. The reconfigurable buffer circuit has an output buffer that outputs a buffered output signal corresponding to an input signal. The reconfigurable buffer control circuit also has a control circuit that receives and stores an inputted control parameter, and receives at least one control signal from a control signal source. Based on the stored control parameter and the at least one control signal received from the control signal source, the control circuit produces the input signal.

Abstract: This application describes a peripheral cell structure for VLSI chips that requires the use of standard cells having both input and output capability connected to nearly all of the signal carrying pins. The cells function is alterable (to input or output and to where the data input signals originate) by control signals which may originate with a control register. The clock input signal is split into two independent signals to selectively disable the input or output registers, thus allowing the control register to be changed without affecting the contents of the other two registers. An early signal is also provided to prepare for mode changes.

Abstract: An improved ring oscillator for VLSI chips is shown, formed at the chip periphery. It may have specific initiation gates and have additional parasitic capacitance added to the ring to enhance accuracy. The circuit elements used for the ring are the same as those used for more centralized circuits.

Abstract: A frequency shift key receiver includes a phase velocity sign detector which detects whether a FSK modulated input signal has a frequency (f.sub.FSK) which is greater than or less than a reference frequency (f.sub.0) of a REF signal. The phase velocity sign detector includes a sequence generator which generates a two bit binary code which represents the phase angle between the FSK and REF signals. The sequence of the code indicates the sign of the phase velocity between the FSK and REF signals. The phase velocity sign detector includes a sequence detector which provides an output signal indicating whether the FSK signal has a frequency greater than or less than the REF signal based upon the sequence of the code from the sequence generator. The phase velocity sign detector demodulates the FSK signal in the digital domain using circuitry which is completely integrable on a monolithic integrated circuit chip.

Abstract: A frequency shift key demodulator produces an output data stream based upon whether a FSK modulated input signal has a frequency (f.sub.FSK) which is greater than or less than a reference frequency (f.sub.0) of a reference (REF) signal. The demodulator includes a sequence generator which generates a two bit binary code which represents the phase angle between the FSK and REF signals. The sequence of the code indicates the sign of the phase velocity between the FSK and REF signals. The demodulator also includes first and second sequence detectors, first and second integrating shift registers, and a decision circuit. The first sequence detector provides an output signal to the first shift register indicating that the FSK signal has a frequency less than the REF signal based upon detection of a first predetermined sequence of the code from the sequence generator.