Abstract: A signal interfacing technique for connecting signals between a signal processing device and a MIMO radio integrated circuit (IC) involving multiplexing two or more signals on a connection pin between the radio IC and a signal processing device. According to one technique, transmit and receive signals are multiplexed such that during a transmit mode a transmit signal is coupled on the connection pin from the signal processing device to the radio IC, and during a receive mode a receive signal is coupled from the radio IC on the connection pin to the signal processing device. According to another technique, in-phase (I) and quadrature (Q) signals are multiplexed on a connection pin during both transmit and receive modes.

Abstract: A signal interfacing technique for connecting signals between a signal processing device and a MIMO radio integrated circuit (IC) involving multiplexing two or more signals on a connection pin between the radio IC and a signal processing device. According to one technique, transmit and receive signals are multiplexed such that during a transmit mode a transmit signal is coupled on the connection pin from the signal processing device to the radio IC, and during a receive mode a receive signal is coupled from the radio IC on the connection pin to the signal processing device. According to another technique, in-phase (I) and quadrature (Q) signals are multiplexed on a connection pin during both transmit and receive modes.

Abstract: A signal interfacing technique for connecting signals between a signal processing device and a radio integrated circuit (IC) involving multiplexing two or more signals on a connection pin between the radio IC and a signal processing device. According to one technique, transmit and receive signals are multiplexed such that during a transmit mode a transmit signal is coupled on the connection pin from the signal processing device to the radio IC, and during a receive mode a receive signal is coupled from the radio IC on the connection pin to the signal processing device. According to another technique, in-phase (I) and quadrature (Q) signals are multiplexed on a connection pin during both transmit and receive modes.

Abstract: There is a desire to provide a testing method and apparatus that can be successfully integrated into a PLL and PLL-like circuits (e.g. frequency synthesizers, delay lock loops, etc.). It is desirable that the PLL or PLL-like circuit integrated with testing apparatus does not suffer from performance degradations during nominal (mission mode) operation. Furthermore, it is desirable that the PLL and the testing apparatus share the same interface. In order to produce a PLL having integrated testing apparatus, without having the PLL suffer severe performance degradations during nominal operation nor having the combination of the PLL and testing apparatus be unnecessarily large, a modified PLL integrated with testing apparatus is provided.

Abstract: A signal interfacing technique for connecting signals between a signal processing device and a radio integrated circuit (IC) involving multiplexing two or more signals on a connection pin between the radio IC and a signal processing device. According to one technique, transmit and receive signals are multiplexed such that during a transmit mode a transmit signal is coupled on the connection pin from the signal processing device to the radio IC, and during a receive mode a receive signal is coupled from the radio IC on the connection pin to the signal processing device. According to another technique, in-phase (I) and quadrature (Q) signals are multiplexed on a connection pin during both transmit and receive modes.

Abstract: There is a desire to provide a testing method and apparatus that can be successfully integrated into a PLL and PLL-like circuits (e.g. frequency synthesizers, delay lock loops, etc.). It is desirable that the PLL or PLL-like circuit integrated with testing apparatus does not suffer from performance degradations during nominal (mission mode) operation. Furthermore, it is desirable that the PLL and the testing apparatus share the same interface. In order to produce a PLL having integrated testing apparatus, without having the PLL suffer severe performance degradations during nominal operation nor having the combination of the PLL and testing apparatus be unnecessarily large, a modified PLL integrated with testing apparatus is provided.

Abstract: Disclosed herein is a mechanism for use in a data processing system for recovering from errors detected when reading data from an array. At least two arrays, each of which may be a distinct portion of a single physical array, contain identical data. When data is written, it is written into both arrays. When data is read, it is read from one of the arrays. If an error is detected on readout, there will be a system retry and the other array will be accessed at the next read request. So long as no errors are detected, each successive read will be from the same array. An error detected on readout will cause the next read operation to access the other array.