Patents by Inventor Michael F. Wall
Michael F. Wall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5331215Abstract: A synaptic array according to the present invention comprises a plurality of electrically-adaptable elements. Electrons may be placed onto and removed from a floating node in each electrically adaptable element associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals generated in response to an adapt signal. The inputs to all synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The current supplied to all amplifiers in a column is commonly provided by a sense line.Type: GrantFiled: July 30, 1992Date of Patent: July 19, 1994Assignee: Synaptics, IncorporatedInventors: Timothy P. Allen, Janeen D. W. Anderson, Carver A. Mead, Federico Faggin, John C. Platt, Michael F. Wall
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Patent number: 5270963Abstract: The present invention is a method and apparatus for performing neighborhood processing operations on an n dimensional processing plane. In a simple, two dimensional, example, an M by N processing plane is successively scanned by rows. The output information from each row is presented on column lines. The analog data resulting from a fixed number of successive scans are temporarily held in a multi-stage analog buffer. A computing array is configured to perform the neighborhood operations or other limited co-operand operations on the shifted data. The computing array examines information from a slice made up of selected numbers of successive rows of the entire array, performs the operations on that portion, and provides a series of output signals representative of the result.Type: GrantFiled: July 6, 1990Date of Patent: December 14, 1993Assignee: Synaptics, IncorporatedInventors: Timothy P. Allen, Michael F. Wall, Federico Faggin
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Patent number: 5165054Abstract: A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.Type: GrantFiled: December 18, 1990Date of Patent: November 17, 1992Assignee: Synaptics, IncorporatedInventors: John C. Platt, Michael F. Wall, Glenn E. Gribble, Carver A. Mead
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Patent number: 5160899Abstract: An adaptable current mirror includes first and second MOS transistors. The first MOS transistor has its gate connected to its drain. A MOS capacitor structure is connected in series between the gate of the first MOS transistor and the gate of the second MOS transistor. Electrons may be placed onto and removed in an analog manner from a floating node associated with the second MOS transistor, usually the gate of the transistor, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. A plurality of adaptable current mirrors communicating with a plurality of current-carrying lines may be employed for indicating the output of the one of the plurality of current-carrying lines through which the most current is flowing.Type: GrantFiled: October 22, 1991Date of Patent: November 3, 1992Assignee: Synaptics, IncorporatedInventors: Janeen D. W. Anderson, Carver A. Mead, Timothy P. Allen, Michael F. Wall
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Patent number: 5146106Abstract: An adaptable MOS winner take all circuit includes a plurality of adaptable current mirrors. Each adaptable current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures. Electrons may be placed onto and removed from a floating node associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.Type: GrantFiled: February 5, 1991Date of Patent: September 8, 1992Assignee: Synaptics, IncorporatedInventors: Janeen D. W. Anderson, Carver A. Mead, Timothy P. Allen, Michael F. Wall
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Patent number: 5126685Abstract: A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.Type: GrantFiled: August 19, 1991Date of Patent: June 30, 1992Assignee: Synaptics, IncorporatedInventors: John C. Platt, Michael F. Wall, Glenn E. Gribble, Carver A. Mead
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Patent number: 5119038Abstract: An MOS current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures in order to adapt the current mirror to supply a desired output current when a particular input calibration current is present.Type: GrantFiled: February 4, 1991Date of Patent: June 2, 1992Assignee: Synaptics, CorporationInventors: Janeen D. W. Anderson, Carver A. Mead, Timothy P. Allen, Michael F. Wall
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Patent number: 5107149Abstract: A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.Type: GrantFiled: August 19, 1991Date of Patent: April 21, 1992Assignee: Synaptics, Inc.Inventors: John C. Platt, Michael F. Wall, Glenn E. Gribble, Carver A. Mead
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Patent number: 5059920Abstract: Electrons may be placed onto and removed from a floating node associated with at least one MOS transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.An analog MOS integrated circuit comprises an amplifier circuit having a gain much larger than 1. The inverting input into one stage of this amplifier circuit is a floating node forming the gate of at least one MOS transistor. A first capacitor couples an input of the circuit to this floating node. Electrical semiconductor structures are provided for both linearly adding and removing charge from the floating gate, thus allowing the offset voltage of the amplifier to be adapted.Type: GrantFiled: May 18, 1990Date of Patent: October 22, 1991Assignee: Synaptics, IncorporatedInventors: Janeen D. W. Anderson, Carver A. Mead, Timothy P. Allen, Michael F. Wall