Abstract: A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units during a thread execution period. The thread execution period is divided among phases, and each of the data units processed by a thread is processed by a different one of the phases.

Abstract: A mechanism to process units of data associated with a dependent data stream using different threads of execution and a common data structure in memory. Accessing the common data structure in memory for the processing uses a single read operation and a single write operation. The folding of multiple read-modify-write memory operations in such a manner for multiple multi-threaded stages of processing includes controlling a first stage, which operates on the same data unit as a second stage to pass context state information to the second stage for coherency.

Abstract: A substrate is provided with vias communicating with surface contacts or bumps. Joining material paste is forced through holes in a screen onto an area array of the contacts on the substrate then the screen is biased against the substrate as the paste is heated and cooled to transfer the joining material onto the contacts. Alternately, joining material paste is forced into the screen and then a substrate is placed onto the screen with an area array of bump contacts of the substrate in contact with the solder paste, and then the paste is heated and cooled to transfer the material onto the bumps. The joining material may be a solder paste, conductive adhesive paste, or transient liquid bond paste. The substrate may be a semiconductor chip substrate, flexible or rigid organic substrate, or a metal substrate coated to form a dielectric surface. Also, the substrate may be a computer chip, chip carrier substrate or a circuit board substrate.

Abstract: Scheduling the processing of threads by scheduling a datagram from an input queue among a plurality of input queues to a thread for processing. The scheduling includes computing an output position in an output queue, communicating with a plurality of threads for processing, and assigning the datagram to one of said plurality of threads for processing. After processing the datagram, the processing thread enqueus the datagram in the output queues at the output position specified by the scheduled output position.

Abstract: A method and structure for a solder interconnection, using solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate is disclosed. After a solder ball has been formed using standard methods it is reflowed to give the solder ball a smooth surface. A layer of low melting point metal, such as, bismuth, indium or tin, preferably, pure tin, is deposited on the top of the solder balls. This structure results in localizing of the eutectic alloy, formed upon subsequent low temperature joining cycle, to the top of the high melting solder ball even after multiple low temperature reflow cycles. This method does not need tinning of the substrate to which the chip is to be joined, which makes this method economical. It has also been noticed that whenever temperature is raised slightly above the eutectic temperature, the structure always forms a liquid fillet around the joint with copper wires.

Abstract: A pulley guides a cable on an overhead framework structure which is suspended from a ceiling by a threaded rod. The pulley includes a guide structure which guides the cable longitudinally through the pulley, and further includes a bracket structure which mounts the guide structure on the threaded rod. The guide structure can be mounted on the threaded rod in a first position in which a cable can be moved transversely into and out of the guide structure, and can be alternatively mounted on the threaded rod in a second position in which the cable cannot be moved transversely into or out of the guide structure.

Abstract: A method and structure for a solder interconnection, using solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate is disclosed. After a solder ball has been formed using standard methods it is reflowed to give the solder ball a smooth surface. A layer of low melting point metal, such as, bismuth, indium or tin, preferably, pure tin, is deposited on the top of the solder balls. This structure results in localizing of the eutectic alloy, formed upon subsequent low temperature joining cycle, to the top of the high melting solder ball even after multiple low temperature reflow cycles. This method does not need tinning of the substrate to which the chip is to be joined, which makes this method economical. It has also been noticed that whenever temperature is raised slightly above the eutectic temperature, the structure always forms a liquid fillet around the joint with copper wires.

Abstract: A telephone system with a caller ID logging feature includes a plurality of telephone stations which share a plurality of telephone lines connected to the telephone system. Each one of the plural telephone lines is associated with one or more of the telephone stations. A control processor (CPU) monitors the incoming calls on the telephone lines connected to the telephone system, and also receives caller ID information from the Central Office of the telephone service provider. For unanswered incoming calls and answered calls which are to be stored, the CPU stores the associated caller ID information in a memory as a caller ID record including data indicating the telephone lines on which the incoming call was received. The stored caller ID records for each telephone line are accessible from telephone stations that are associated with that telephone line. Therefore, only one record is required which all users may access, thereby increasing the efficiency of the memory over prior art systems.

Abstract: An electronic package comprising an integrated circuit chip and a flip chip solder bonded thereto is provided. The integrated circuit chip has circuitry over a major surface thereof and has peripheral wire or tab bond pads surrounding an array of C4 connection pads located over this major surface. A flip chip is solder bonded to the C4 connection pads.

Abstract: An information processing system adapted for use in conjunction with a telephone communication system. The information processing system includes a caller identification signal receiver, a timed switching device, and a call forwarding device. When no incoming call is being received, the timed switching device is in a first, open state, such that a circuit between the telephone line and the call forwarding device is interrupted. Upon receipt of an incoming call on the telephone line, the timed switching device and the caller identification signal receiver are activated. The timed switching device enters a second, closed state after a finite amount of time has elapsed such as, for example, several seconds, thereby allowing sufficient time for the caller identification signal to arrive on the incoming telephone line.

Abstract: A process within substrate is provided with vias communicating with surface contacts or bumps. Joining material paste is forced through holes in a screen onto an area array of the contacts on the substrate then the screen is biased against the substrate as the paste is heated and cooled to transfer the joining material onto the contacts. Alternately, joining material paste is forced into the screen and then a substrate is placed onto the screen with an area array of bump contacts of the substrate in contact with the solder paste, and then the paste is heated and cooled to transfer the material onto the bumps. The joining material may be a solder paste, conductive adhesive paste, or transient liquid bond paste. The substrate may be a semiconductor chip substrate, flexible or rigid organic substrate, or a metal substrate coated to form a dielectric surface. Also, the substrate may be a computer chip, chip carrier substrate or a circuit board substrate.

Abstract: The present method employs a first plating resist for forming circuit lines on a carrier substrate. While the plating resist is still in place a metal, such as nickel, is deposited on top of the circuit lines. A second plating resist is employed for plating solder on the circuit lines at solder sites. At this stage additional solder can be deposited at each solder site to provide or supplement the necessary low melt solder required for forming a solder joint. The first and second resists along with solder thereon are then stripped and copper foil on the carrier substrate is etched away around the circuit lines. A soldermask is then formed on the carrier substrate over the circuit lines except for circuit lines in the chip sites. The soldermask has a single large opening at each chip site which has lateral dimensions which are slightly larger than the lateral dimensions of the chip to be connected at the chip site.

Abstract: A structure and a method is disclosed for making a laminated circuit carrier card for the purpose of making a Direct Chip Attached Module (DCAM) with low cost and high reliability. The carrier is made using an organic or an inorganic laminated carrier having at least one surface available for direct chip mount. The chip has at least one solder ball with a cap of low melting point metal. The surface of the carrier has electrical features that are directly connected to the low melting point metal on the solder ball of the chip to form the eutectic and this way the chip is directly attached to the carrier.

Abstract: Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.

Abstract: Small, closely spaced deposits of solder materials may be formed with high volumetric accuracy and uniformity of shape by depositing a layer of conductive material over surfaces of a dielectric layer having apertures or recesses (e.g. blind apertures) and conductors and/or pads exposed by those apertures or recesses, masking regions of the conductive material with a further patterned dielectric layer, electroplating solder materials onto regions of the conductive material exposed by the mask, removing the mask and portions of the conductive material by selective etching and reflowing solder away from at least a portion of the surfaces of the apertured dielectric layer. Uniformity of electroplating within blind apertures is enhanced by a combination of fluid jet sparging and cathode agitation. Excess conductor material in the resulting solder deposit can be avoided by replacing conductor material with a constituent component of a solder material in an immersion bath prior to electroplating.

Abstract: The present method employs a first plating resist for forming circuit lines on a carrier substrate. While the plating resist is still in place a metal, such as nickel, is deposited on top of the circuit lines. A second plating resist is employed for plating solder on the circuit lines at solder sites. At this stage additional solder can be deposited at each solder site to provide or supplement the necessary low melt solder required for forming a solder joint. The first and second resists along with solder thereon are then stripped and copper foil on the carrier substrate is etched away around the circuit lines. A soldermask is then formed on the carrier substrate over the circuit lines except for circuit lines in the chip sites. The soldermask has a single large opening at each chip site which has lateral dimensions which are slightly larger than the lateral dimensions of the chip to be connected at the chip site.

Abstract: A clock output signal is aligned in phase to conicide with the phase of signals derived from a master clock. In the event that there is a malfunction of the master, standby control circuitry modifies the phase of the clock output signal incremental quantities until it is in phase with the phase of signals from a standby clock. The clock output signal is thereafter maintained aligned in phase to coincide with the phase of the signals derived from the standby clock.